141 lines
7.3 KiB
Tcl
141 lines
7.3 KiB
Tcl
#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# Timing constraints exclusive to X410. These should be used
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# in conjunction with ./common.xdc
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#
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###############################################################################
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# DB GPIO
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# This interface is defined as system synchronous to pll_ref_clk.
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# Some timing constants in this section are declared in
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# <repo>/fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc
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###############################################################################
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# Set output constraints for all ports.
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set db_gpio_ports [get_ports {DB0_GPIO[*] DB1_GPIO[*]}]
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set_output_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_fpga_min_out $db_gpio_ports
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set_output_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_fpga_max_out $db_gpio_ports
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# Output enable signal is available one clock cycle ahead of valid data, this
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# enables the use of multi-cycle paths.
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set db_gpio_out_en_regs [get_cells -hierarchical -filter \
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{PRIMITIVE_TYPE =~ REGISTER.*.* && NAME =~ "*bytestream_output_enable*"}]
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set_multicycle_path 2 -setup -from $db_gpio_out_en_regs -to $db_gpio_ports
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set_multicycle_path 1 -hold -from $db_gpio_out_en_regs -to $db_gpio_ports
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# Calculate output delays back from capturing edge, add board delay and clock
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# difference.
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# Assume worst case as data being generated late and receiving an early clock:
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# - Max CPLD TCO
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# - Max data propagation delay
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# - Max CPLD clock propagation delay and minimum FPGA clock propagation delay
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# - Maximum delay from MC100EPT23 clock buffer
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set_input_delay -clock pll_ref_clk \
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-max [expr {$pll_ref_clk_period - $db_gpio_cpld_max_out + $db_gpio_board_max_delay \
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+ $db_cpld_prc_clock_prop_max - $fpga_prc_clock_prop_min + $clock_translate_max}] \
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$db_gpio_ports
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# Negate minimum output delay as it is defined from the change to the start
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# clock edge.
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# Assume worst case as data being generated early and receiving an late clock:
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# - Min CPLD TCO
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# - Min data propagation delay (0)
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# - Min CPLD clock propagation delay and max FPGA clock propagation delay
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set_input_delay -clock pll_ref_clk \
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-min [expr {- $db_gpio_cpld_min_out \
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- $db_gpio_board_min_delay \
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- $db_cpld_prc_clock_prop_min + $fpga_prc_clock_prop_max}] \
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$db_gpio_ports
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###############################################################################
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# x410_ps_rfdc_bd
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###############################################################################
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# This property tells Vivado that we require the clocks generated by the RFDC MMCM to be well
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# aligned. We have synchronous clock domain crossings between these clocks that can have
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# large hold violations after placement due to uneven clock loading.
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# The constraint CLOCK_DELAY_GROUP has to be applied on the clock nets.
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# These nets are connected to the outputs of the clock buffers, which are driven by the MMCM.
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# Search the nets begining from the MMCM outputs to find the clock buffers outputs.
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set rfdc_mmcm [get_cells -hierarchical -filter { PRIMITIVE_TYPE == CLOCK.PLL.MMCME4_ADV && NAME =~ *rfdc/data_clock_mmcm* } ]
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set mmcm_clkout_pins [get_pins -of_objects $rfdc_mmcm -regexp -filter {NAME =~ ".*CLKOUT[0-4]"}]
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set mmcm_clkout_nets [get_nets -of_objects $mmcm_clkout_pins]
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set clkbuf_in_pins [get_pins -leaf -of_objects $mmcm_clkout_nets -filter {DIRECTION == IN}]
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set clkbuf_cells [get_cells -of_objects $clkbuf_in_pins]
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set clkbuf_out_pins [get_pins -of_objects $clkbuf_cells -filter {DIRECTION == OUT}]
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set clkbuf_out_nets [get_nets -of_objects $clkbuf_out_pins]
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set_property CLOCK_DELAY_GROUP DataClkGroup $clkbuf_out_nets
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# We treat rfdc_clk buffers as asynchronous, with knowledge that
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# code clocked in this domain will be reset after this clocked is enabled. This
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# will make timing easier to meet on these clock domains.
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# set_false_path -from [get_cells -hierarchical -regexp -filter {NAME =~ .*/rfdc/clock_gates_0/.*rEnableRfdc\dBufg.*_reg}]
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set_false_path -from [get_cells -hierarchical -regexp -filter {NAME =~ .*/rfdc/clock_gates_0/.*rEnableDataBufg\dx.*_reg}]
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set_false_path -from [get_cells -hierarchical -regexp -filter {NAME =~ .*/rfdc/clock_gates_0/.*rEnableRfdcBufg\dx.*_reg}]
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###############################################################################
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# SPLL SYSREF Capture
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###############################################################################
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# SYSREF is generated by the LMK04832 clocking chip (SPLL), which also produces
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# the PLL reference clock (PRC) used to generate data clocks with a MMCM. Both
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# SYSREF and PLL reference clock are directly fed into the RFSoC.
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# The LMK04832 is configured to output all clocks synchronized to the
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# rising edge of SYSREF. SYSREF is first captured by the FPGA fabric in the
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# PRC clock domain (MMCM's PRC output) on the falling edge to meet setup and
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# hold times. Afterwards it is captured with a double synchronizer and then
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# transferred to the RFDC clock domain. Both SYSREF versions (PRC and RFDC)
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# are used by downstream logic for sync purposes.
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# The highest PRC frequency supported in MPM (64 MHz) is used for
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# timing constraints.
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# Set SYSREF LMK Delay to 0 ns as we assume rising edge alignment from the
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# LMK04832 chip.
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set sysref_lmk_delay 0
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#
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# These are the signals' lengths and corresponding delays (assuming 170 ps/in):
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# - SYSREF --> 5794 mils (5.794 inches) = 0.985 ns
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# - PRC --> 5668 mils (5.668 inches) = 0.964 ns
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#
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# For min/max input delay calculations, it is assumed min prop. delay of 0 ns,
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# which essentially over-constrains SYSREF.
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#
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# The max input delay is the latest that SYSREF may arrive w.r.t PRC, and it is
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# calculated as follows:
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# Input delay (max) = SYSREF's LMK delay + SYSREF prop. delay (max)
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# - PRC prop. delay (min)
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set sysref_max_input_delay [expr {$sysref_lmk_delay + 0.985 - 0}]
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#
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# The min input delay is the earliest that SYSREF may arrive w.r.t PRC, and it
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# is calculated as follows:
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# Input delay (min) = SYSREF's LMK delay + SYSREF prop. delay (min)
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# - PRC prop. delay (min)
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set sysref_min_input_delay [expr {$sysref_lmk_delay + 0 - 0.964}]
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set_input_delay -clock pll_ref_clk -max $sysref_max_input_delay [get_ports {SYSREF_FABRIC_P}]
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set_input_delay -clock pll_ref_clk -min $sysref_min_input_delay [get_ports {SYSREF_FABRIC_P}]
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###############################################################################
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# SPI to MB CPLD (PL)
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# This interface is defined as system synchronous to pll_ref_clk.
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###############################################################################
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# The output delays are chosen to allow a large time window of valid data for
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# the MB CPLD logic.
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set spi_min_out_delay 0.000
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set spi_max_out_delay 11.000
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# Set output constraints for all ports.
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set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}]
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set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports
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set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports
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# Force SPI registers into IOB.
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set_property IOB TRUE [get_cells "cpld_interface_i/ctrlport_spi_master_i/simple_spi_core_64bit_i/sclk_reg"]
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set_property IOB TRUE [get_cells "cpld_interface_i/ctrlport_spi_master_i/simple_spi_core_64bit_i/mosi_reg"]
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