34 lines
1.3 KiB
Systemverilog
34 lines
1.3 KiB
Systemverilog
//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: eth_constants (Header File)
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//
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// Description:
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// Holds register offsets for the Ethernet Interface
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// NOTE: These depend on the following parameters
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// Parameters:
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// REG_AWIDTH - How wide the register window is in bits
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// BASE - Base address added to the offsets here
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// REGISTER OFFSETS
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// Allocate one full page for MAC
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localparam [REG_AWIDTH-1:0] REG_MAC_LSB = BASE + 'h0000;
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localparam [REG_AWIDTH-1:0] REG_MAC_MSB = BASE + 'h0004;
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// Source IP address
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localparam [REG_AWIDTH-1:0] REG_IP = BASE + 'h1000;
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// Source UDP Port
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localparam [REG_AWIDTH-1:0] REG_UDP = BASE + 'h1004;
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// Registers for Internal/Bridge Network Mode in CPU
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localparam [REG_AWIDTH-1:0] REG_BRIDGE_MAC_LSB = BASE + 'h1010;
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localparam [REG_AWIDTH-1:0] REG_BRIDGE_MAC_MSB = BASE + 'h1014;
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localparam [REG_AWIDTH-1:0] REG_BRIDGE_IP = BASE + 'h1018;
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localparam [REG_AWIDTH-1:0] REG_BRIDGE_UDP = BASE + 'h101c;
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localparam [REG_AWIDTH-1:0] REG_BRIDGE_ENABLE = BASE + 'h1020;
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localparam [REG_AWIDTH-1:0] REG_CHDR_DROPPED = BASE + 'h1030;
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localparam [REG_AWIDTH-1:0] REG_CPU_DROPPED = BASE + 'h1034;
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localparam [REG_AWIDTH-1:0] REG_PAUSE = BASE + 'h1038;
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