Wade Fife
0c6f2627a5
Fixes various synthesis/simulation warnings that were being generated due to incorrectly sized constants. Original-commit: 00f683c91486647f1711eb4c0b0a917078d29652
382 lines
18 KiB
Verilog
382 lines
18 KiB
Verilog
//
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// Copyright 2018 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: chdr_crossbar_nxn
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// Description:
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// This module implements a full-bandwidth NxN crossbar with N input and output ports
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// for CHDR traffic. It supports multiple optimization strategies for performance,
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// area and timing tradeoffs. It uses AXI-Stream for all of its links. The crossbar
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// has a dynamic routing table based on a Content Addressable Memory (CAM). The SID
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// is used to determine the destination of a packet and the routing table contains
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// a re-programmable SID to crossbar port mapping. The table is programmed using
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// special route config packets on the data input ports or using an optional
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// management port.
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// The topology, routing algorithms and the router architecture is
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// described in README.md in this directory.
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// Parameters:
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// - CHDR_W: Width of the AXI-Stream data bus
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// - NPORTS: Number of ports to instantiate
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// - DEFAULT_PORT: The failsafe port to forward a packet to is SID mapping is missing
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// - MTU: log2 of max packet size (in words)
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// - ROUTE_TBL_SIZE: log2 of the number of mappings that the routing table can hold
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// at any time. Mapping values are maintained in a FIFO fashion.
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// - MUX_ALLOC: Algorithm to allocate the egress MUX
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// * PRIO: Priority based. Lower port numbers have a higher priority
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// * ROUND-ROBIN: Round robin input port allocation
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// - OPTIMIZE: Optimization strategy for performance vs area vs timing tradeoffs
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// * AREA: Attempt to minimize area at the cost of performance (throughput) and/or timing
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// * PERFORMANCE: Attempt to maximize performance at the cost of area and/or timing
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// * TIMING: Attempt to maximize Fmax at the cost of area and/or performance
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// - NPORTS_MGMT: Number of ports with management endpoint. The first NPORTS_MGMT ports will
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// have the management port instantiated
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// - EXT_RTCFG_PORT: Enable a side-channel AXI-Stream management port to configure the
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// routing table
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// Signals:
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// - s_axis_*: Slave port for router (flattened)
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// - m_axis_*: Master port for router (flattened)
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// - s_axis_mgmt_*: Management slave port
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// - device_id: The ID of the device that has instantiated this module
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//
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module chdr_crossbar_nxn #(
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parameter [15:0] PROTOVER = {8'd1, 8'd0},
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parameter CHDR_W = 64,
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parameter [7:0] NPORTS = 8,
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parameter [7:0] DEFAULT_PORT = 0,
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parameter MTU = 10,
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parameter ROUTE_TBL_SIZE = 6,
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parameter MUX_ALLOC = "ROUND-ROBIN",
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parameter OPTIMIZE = "AREA",
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parameter [7:0] NPORTS_MGMT = NPORTS,
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parameter [0:0] EXT_RTCFG_PORT = 0
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) (
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input wire clk,
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input wire reset,
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// Device info
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input wire [15:0] device_id,
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// Inputs
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input wire [(CHDR_W*NPORTS)-1:0] s_axis_tdata,
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input wire [NPORTS-1:0] s_axis_tlast,
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input wire [NPORTS-1:0] s_axis_tvalid,
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output wire [NPORTS-1:0] s_axis_tready,
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// Output
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output wire [(CHDR_W*NPORTS)-1:0] m_axis_tdata,
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output wire [NPORTS-1:0] m_axis_tlast,
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output wire [NPORTS-1:0] m_axis_tvalid,
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input wire [NPORTS-1:0] m_axis_tready,
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// Router config management port
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input wire ext_rtcfg_stb,
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input wire [15:0] ext_rtcfg_addr,
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input wire [31:0] ext_rtcfg_data,
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output wire ext_rtcfg_ack
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);
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// ---------------------------------------------------
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// RFNoC Includes
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// ---------------------------------------------------
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`include "../core/rfnoc_chdr_utils.vh"
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`include "../core/rfnoc_chdr_internal_utils.vh"
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localparam NPORTS_W = $clog2(NPORTS);
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localparam EPID_W = 16;
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localparam [17:0] EXT_INFO = {1'b0, EXT_RTCFG_PORT, NPORTS_MGMT, NPORTS};
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localparam [0:0] PKT_ST_HEAD = 1'b0;
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localparam [0:0] PKT_ST_BODY = 1'b1;
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// The compute_mux_alloc function is the switch allocation function for the MUX
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// i.e. it chooses which input port reserves the output MUX for packet transfer.
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function [NPORTS_W-1:0] compute_mux_alloc;
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input [NPORTS-1:0] pkt_waiting;
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input [NPORTS_W-1:0] last_alloc;
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reg signed [NPORTS_W:0] i;
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begin
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compute_mux_alloc = last_alloc;
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for (i = NPORTS-1; i >= 0; i=i-1) begin
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if (MUX_ALLOC == "PRIO") begin
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// Priority. Lower port index gets a higher priority.
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if (pkt_waiting[i])
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compute_mux_alloc = i;
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end else begin
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// Round-robin
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if (pkt_waiting[(last_alloc + i + 1) % NPORTS])
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compute_mux_alloc = (last_alloc + i + 1) % NPORTS;
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end
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end
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end
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endfunction
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wire [NPORTS-1:0] rtcfg_req_wr;
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wire [(16*NPORTS)-1:0] rtcfg_req_addr;
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wire [(32*NPORTS)-1:0] rtcfg_req_data;
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wire [NPORTS-1:0] rtcfg_resp_ack;
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wire [(EPID_W*NPORTS)-1:0] find_tdata;
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wire [NPORTS-1:0] find_tvalid;
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wire [NPORTS-1:0] find_tready;
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wire [(NPORTS_W*NPORTS)-1:0] result_tdata;
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wire [NPORTS-1:0] result_tkeep;
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wire [NPORTS-1:0] result_tvalid;
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wire [NPORTS-1:0] result_tready;
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// Instantiate a single CAM-based routing table that will be shared between all
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// input ports. Configuration and lookup is performed using an AXI-Stream iface.
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// If multiple packets arrive simultaneously, only the headers of those packets will
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// be serialized in order to arbitrate this map. Selection is done round-robin.
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chdr_xb_routing_table #(
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.SIZE(ROUTE_TBL_SIZE), .NPORTS(NPORTS),
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.EXT_INS_PORT_EN(EXT_RTCFG_PORT)
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) routing_tbl_i (
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.clk (clk ),
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.reset (reset ),
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.port_req_wr (rtcfg_req_wr ),
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.port_req_addr (rtcfg_req_addr),
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.port_req_data (rtcfg_req_data),
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.port_resp_ack (rtcfg_resp_ack),
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.ext_req_wr (ext_rtcfg_stb ),
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.ext_req_addr (ext_rtcfg_addr),
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.ext_req_data (ext_rtcfg_data),
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.ext_resp_ack (ext_rtcfg_ack ),
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.axis_find_tdata (find_tdata ),
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.axis_find_tvalid (find_tvalid ),
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.axis_find_tready (find_tready ),
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.axis_result_tdata (result_tdata ),
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.axis_result_tkeep (result_tkeep ),
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.axis_result_tvalid(result_tvalid ),
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.axis_result_tready(result_tready )
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);
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wire [CHDR_W-1:0] i_tdata [0:NPORTS-1];
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wire [9:0] i_tdest [0:NPORTS-1];
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wire [1:0] i_tid [0:NPORTS-1];
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wire i_tlast [0:NPORTS-1];
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wire i_tvalid [0:NPORTS-1];
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wire i_tready [0:NPORTS-1];
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wire [CHDR_W-1:0] buf_tdata [0:NPORTS-1];
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wire [NPORTS_W-1:0] buf_tdest [0:NPORTS-1], buf_tdest_tmp[0:NPORTS-1];
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wire buf_tkeep [0:NPORTS-1];
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wire buf_tlast [0:NPORTS-1];
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wire buf_tvalid[0:NPORTS-1];
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wire buf_tready[0:NPORTS-1];
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wire [CHDR_W-1:0] swi_tdata [0:NPORTS-1];
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wire [NPORTS_W-1:0] swi_tdest [0:NPORTS-1];
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wire swi_tlast [0:NPORTS-1];
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wire swi_tvalid[0:NPORTS-1];
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wire swi_tready[0:NPORTS-1];
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wire [(CHDR_W*NPORTS)-1:0] swo_tdata [0:NPORTS-1], muxi_tdata [0:NPORTS-1];
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wire [NPORTS-1:0] swo_tlast [0:NPORTS-1], muxi_tlast [0:NPORTS-1];
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wire [NPORTS-1:0] swo_tvalid[0:NPORTS-1], muxi_tvalid[0:NPORTS-1];
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wire [NPORTS-1:0] swo_tready[0:NPORTS-1], muxi_tready[0:NPORTS-1];
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genvar n, i, j;
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generate
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for (n = 0; n < NPORTS; n = n + 1) begin: i_ports
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// For each input port, first check if we have a management packet
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// arriving. If it arrives, the top config commands are extrated, sent to the
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// routing table for configuration, and the rest of the packet is forwarded
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// down to the router.
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// the router.
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if (n < NPORTS_MGMT) begin
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chdr_mgmt_pkt_handler #(
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.PROTOVER(PROTOVER), .CHDR_W(CHDR_W), .MGMT_ONLY(0)
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) mgmt_ep_i (
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.clk (clk ),
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.rst (reset ),
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.node_info (chdr_mgmt_build_node_info(EXT_INFO, n, NODE_TYPE_XBAR, device_id)),
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.s_axis_chdr_tdata (s_axis_tdata [(n*CHDR_W)+:CHDR_W] ),
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.s_axis_chdr_tlast (s_axis_tlast [n] ),
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.s_axis_chdr_tvalid (s_axis_tvalid[n] ),
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.s_axis_chdr_tready (s_axis_tready[n] ),
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.s_axis_chdr_tuser (1'd0 ),
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.m_axis_chdr_tdata (i_tdata [n] ),
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.m_axis_chdr_tdest (i_tdest [n] ),
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.m_axis_chdr_tid (i_tid [n] ),
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.m_axis_chdr_tlast (i_tlast [n] ),
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.m_axis_chdr_tvalid (i_tvalid [n] ),
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.m_axis_chdr_tready (i_tready [n] ),
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.ctrlport_req_wr (rtcfg_req_wr [n] ),
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.ctrlport_req_rd (/* unused */ ),
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.ctrlport_req_addr (rtcfg_req_addr[(n*16)+:16] ),
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.ctrlport_req_data (rtcfg_req_data[(n*32)+:32] ),
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.ctrlport_resp_ack (rtcfg_resp_ack[n] ),
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.ctrlport_resp_data (32'h0 /* unused */ ),
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.op_stb (/* unused */ ),
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.op_dst_epid (/* unused */ ),
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.op_src_epid (/* unused */ ),
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.op_data (/* unused */ )
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);
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end else begin
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assign i_tdata [n] = s_axis_tdata [(n*CHDR_W)+:CHDR_W];
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assign i_tid [n] = CHDR_MGMT_ROUTE_EPID;
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assign i_tdest [n] = 10'd0; // Unused
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assign i_tlast [n] = s_axis_tlast [n];
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assign i_tvalid [n] = s_axis_tvalid[n];
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assign s_axis_tready[n] = i_tready [n];
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assign rtcfg_req_wr [n] = 1'b0;
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assign rtcfg_req_addr[(n*16)+:16] = 16'h0;
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assign rtcfg_req_data[(n*32)+:32] = 32'h0;
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end
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// Ingress buffer module that does the following:
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// - Stores and gates an incoming packet
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// - Looks up destination in routing table and attaches a tdest for the packet
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chdr_xb_ingress_buff #(
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.WIDTH(CHDR_W), .MTU(MTU), .DEST_W(NPORTS_W), .NODE_ID(n)
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) buf_i (
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.clk (clk ),
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.reset (reset ),
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.s_axis_chdr_tdata (i_tdata [n] ),
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.s_axis_chdr_tdest (i_tdest [n][NPORTS_W-1:0] ),
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.s_axis_chdr_tid (i_tid [n] ),
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.s_axis_chdr_tlast (i_tlast [n] ),
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.s_axis_chdr_tvalid (i_tvalid [n] ),
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.s_axis_chdr_tready (i_tready [n] ),
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.m_axis_chdr_tdata (buf_tdata [n] ),
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.m_axis_chdr_tdest (buf_tdest_tmp[n] ),
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.m_axis_chdr_tkeep (buf_tkeep [n] ),
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.m_axis_chdr_tlast (buf_tlast [n] ),
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.m_axis_chdr_tvalid (buf_tvalid [n] ),
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.m_axis_chdr_tready (buf_tready [n] ),
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.m_axis_find_tdata (find_tdata [(n*EPID_W)+:EPID_W] ),
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.m_axis_find_tvalid (find_tvalid [n] ),
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.m_axis_find_tready (find_tready [n] ),
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.s_axis_result_tdata (result_tdata [(n*NPORTS_W)+:NPORTS_W]),
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.s_axis_result_tkeep (result_tkeep [n] ),
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.s_axis_result_tvalid(result_tvalid[n] ),
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.s_axis_result_tready(result_tready[n] )
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);
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assign buf_tdest[n] = buf_tkeep[n] ? buf_tdest_tmp[n] : DEFAULT_PORT[NPORTS_W-1:0];
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// Pipeline state
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axi_fifo #(
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.WIDTH(CHDR_W+1+NPORTS_W), .SIZE(1)
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) pipe_i (
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.clk (clk ),
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.reset (reset ),
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.clear (1'b0 ),
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.i_tdata ({buf_tlast[n], buf_tdest[n], buf_tdata[n]}),
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.i_tvalid (buf_tvalid[n] ),
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.i_tready (buf_tready[n] ),
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.o_tdata ({swi_tlast[n], swi_tdest[n], swi_tdata[n]}),
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.o_tvalid (swi_tvalid[n] ),
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.o_tready (swi_tready[n] ),
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.space (/* Unused */ ),
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.occupied (/* Unused */ )
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);
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// Ingress demux. Use the tdest field to determine packet destination
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axis_switch #(
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.DATA_W(CHDR_W), .DEST_W(1), .IN_PORTS(1), .OUT_PORTS(NPORTS), .PIPELINE(1)
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) demux_i (
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.clk (clk ),
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.reset (reset ),
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.s_axis_tdata (swi_tdata [n] ),
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.s_axis_tdest ({1'b0, swi_tdest [n]}),
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.s_axis_tlast (swi_tlast [n] ),
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.s_axis_tvalid (swi_tvalid[n] ),
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.s_axis_tready (swi_tready[n] ),
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.s_axis_alloc (1'b0 ),
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.m_axis_tdata (swo_tdata [n] ),
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.m_axis_tdest (/* Unused */ ),
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.m_axis_tlast (swo_tlast [n] ),
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.m_axis_tvalid (swo_tvalid[n] ),
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.m_axis_tready (swo_tready[n] )
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);
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end
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for (i = 0; i < NPORTS; i = i + 1) begin
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for (j = 0; j < NPORTS; j = j + 1) begin
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assign muxi_tdata [i][j*CHDR_W+:CHDR_W] = swo_tdata [j][i*CHDR_W+:CHDR_W];
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assign muxi_tlast [i][j] = swo_tlast [j][i];
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assign muxi_tvalid[i][j] = swo_tvalid [j][i];
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assign swo_tready [i][j] = muxi_tready[j][i];
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end
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end
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for (n = 0; n < NPORTS; n = n + 1) begin: o_ports
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if (OPTIMIZE == "PERFORMANCE") begin
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// Use the axis_switch module when optimizing for performance
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// This logic has some extra levels of logic to ensure
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// that the switch allocation happens in 0 clock cycles which
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// means that Fmax for this implementation will be lower.
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wire mux_ready = |muxi_tready[n]; // Max 1 bit should be high
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wire mux_valid = |muxi_tvalid[n];
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wire mux_last = |(muxi_tvalid[n] & muxi_tlast[n]);
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// Track the input packet state
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reg [0:0] pkt_state = PKT_ST_HEAD;
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always @(posedge clk) begin
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if (reset) begin
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pkt_state <= PKT_ST_HEAD;
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end else if (mux_valid & mux_ready) begin
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pkt_state <= mux_last ? PKT_ST_HEAD : PKT_ST_BODY;
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end
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end
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// The switch requires the allocation to stay valid until the
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// end of the packet. We also might need to keep the previous
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// packet's allocation to compute the current one
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reg [NPORTS_W-1:0] prev_sw_alloc = {NPORTS_W{1'b0}};
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reg [NPORTS_W-1:0] pkt_sw_alloc = {NPORTS_W{1'b0}};
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wire [NPORTS_W-1:0] muxi_sw_alloc = (mux_valid && pkt_state == PKT_ST_HEAD) ?
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compute_mux_alloc(muxi_tvalid[n], prev_sw_alloc) : pkt_sw_alloc;
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always @(posedge clk) begin
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if (reset) begin
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prev_sw_alloc <= {NPORTS_W{1'b0}};
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pkt_sw_alloc <= {NPORTS_W{1'b0}};
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end else if (mux_valid & mux_ready) begin
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if (pkt_state == PKT_ST_HEAD)
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pkt_sw_alloc <= muxi_sw_alloc;
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if (mux_last)
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prev_sw_alloc <= muxi_sw_alloc;
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end
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end
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axis_switch #(
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.DATA_W(CHDR_W), .DEST_W(1), .IN_PORTS(NPORTS), .OUT_PORTS(1),
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.PIPELINE(0)
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) mux_i (
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.clk (clk ),
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.reset (reset ),
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.s_axis_tdata (muxi_tdata [n] ),
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.s_axis_tdest ({NPORTS{1'b0}} /* Unused */ ),
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.s_axis_tlast (muxi_tlast [n] ),
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.s_axis_tvalid (muxi_tvalid[n] ),
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.s_axis_tready (muxi_tready[n] ),
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.s_axis_alloc (muxi_sw_alloc ),
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.m_axis_tdata (m_axis_tdata [(n*CHDR_W)+:CHDR_W]),
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.m_axis_tdest (/* Unused */ ),
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.m_axis_tlast (m_axis_tlast [n] ),
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.m_axis_tvalid (m_axis_tvalid[n] ),
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.m_axis_tready (m_axis_tready[n] )
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);
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end else begin
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// axi_mux has an additional bubble cycle but the logic
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// to allocate an input port has fewer levels and takes
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// up fewer resources.
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axi_mux #(
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.PRIO(MUX_ALLOC == "PRIO"), .WIDTH(CHDR_W), .SIZE(NPORTS),
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.PRE_FIFO_SIZE(OPTIMIZE == "TIMING" ? 1 : 0), .POST_FIFO_SIZE(1)
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) mux_i (
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.clk (clk ),
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.reset (reset ),
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.clear (1'b0 ),
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.i_tdata (muxi_tdata [n] ),
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.i_tlast (muxi_tlast [n] ),
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.i_tvalid (muxi_tvalid [n] ),
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.i_tready (muxi_tready [n] ),
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.o_tdata (m_axis_tdata [(n*CHDR_W)+:CHDR_W]),
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.o_tlast (m_axis_tlast [n] ),
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.o_tvalid (m_axis_tvalid[n] ),
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.o_tready (m_axis_tready[n] )
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);
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end
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end
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endgenerate
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endmodule
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