63 lines
1.8 KiB
Systemverilog
63 lines
1.8 KiB
Systemverilog
//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_terminator.v
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//
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// Description:
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//
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// Returns an error for all ctrlport requests in given address range.
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//
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// Parameters:
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//
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// START_ADDRESS: First address to generate response for
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// LAST_ADDRESS: Last address (including) to generate response for
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//
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module ctrlport_terminator
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import ctrlport_pkg::*;
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#(
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int START_ADDRESS = 0,
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int LAST_ADDRESS = 32
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)(
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//---------------------------------------------------------------
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// ControlPort slave
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//---------------------------------------------------------------
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input logic ctrlport_clk,
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input logic ctrlport_rst,
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input logic s_ctrlport_req_wr,
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input logic s_ctrlport_req_rd,
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input logic [CTRLPORT_ADDR_W-1:0] s_ctrlport_req_addr,
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input logic [CTRLPORT_DATA_W-1:0] s_ctrlport_req_data,
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output logic s_ctrlport_resp_ack,
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output logic [ CTRLPORT_STS_W-1:0] s_ctrlport_resp_status,
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output logic [CTRLPORT_DATA_W-1:0] s_ctrlport_resp_data
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);
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// Define interfaces
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ctrlport_if s_ctrlport_if(.clk(ctrlport_clk), .rst(ctrlport_rst));
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// Map existing ports to ctrlport_if
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always_comb begin
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s_ctrlport_if.req.wr = s_ctrlport_req_wr;
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s_ctrlport_if.req.rd = s_ctrlport_req_rd;
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s_ctrlport_if.req.addr = s_ctrlport_req_addr;
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s_ctrlport_if.req.data = s_ctrlport_req_data;
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s_ctrlport_resp_ack = s_ctrlport_if.resp.ack;
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s_ctrlport_resp_status = s_ctrlport_if.resp.status;
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s_ctrlport_resp_data = s_ctrlport_if.resp.data;
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end
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// Instantiate ctrlport_if_clk_cross module
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ctrlport_if_terminator #(
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.BASE_ADDRESS(START_ADDRESS),
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.WINDOW_SIZE(LAST_ADDRESS - START_ADDRESS + 1)
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) terminator_inst (
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.s_ctrlport(s_ctrlport_if)
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);
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endmodule
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