45 lines
1.1 KiB
Systemverilog
45 lines
1.1 KiB
Systemverilog
//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_if_terminator
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//
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// Description:
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//
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// Returns an error for all ctrlport requests in given address range.
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//
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// Parameters:
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//
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// BASE_ADDRESS : First address to generate response for.
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// WINDOW_SIZE : Size of the address space.
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// Last address in range will be BASE_ADDRESS + WINDOW_SIZE - 1.
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//
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module ctrlport_if_terminator #(
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int BASE_ADDRESS = 0,
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int WINDOW_SIZE = 32
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)(
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ctrlport_if.slave s_ctrlport
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);
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import ctrlport_pkg::*;
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// drive acknowledgement on requests but not on reset
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always_ff @(posedge s_ctrlport.clk) begin
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if (s_ctrlport.rst) begin
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s_ctrlport.resp.ack <= 1'b0;
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end else if ((s_ctrlport.req.addr >= BASE_ADDRESS) &&
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(s_ctrlport.req.addr < BASE_ADDRESS + WINDOW_SIZE)) begin
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s_ctrlport.resp.ack <= s_ctrlport.req.wr | s_ctrlport.req.rd;
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end else begin
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s_ctrlport.resp.ack <= 1'b0;
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end
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end
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// other outputs are fixed
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assign s_ctrlport.resp.status = STS_CMDERR;
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assign s_ctrlport.resp.data = '0;
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endmodule
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