133 lines
5.1 KiB
YAML
133 lines
5.1 KiB
YAML
# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: >- # Copyright information used in file headers
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Copyright 2023 Ettus Research, a National Instruments Brand
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license: >- # License information used in file headers
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SPDX-License-Identifier: LGPL-3.0-or-later
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version: '1.0' # File version
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chdr_width: 64 # Bit width of the CHDR bus for this image
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device: 'x310'
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default_target: 'X310_HG'
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# A list of all stream endpoints in design
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# ----------------------------------------
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stream_endpoints:
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ep0: # Stream endpoint name
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ctrl: True # Endpoint passes control traffic
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data: True # Endpoint passes data traffic
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buff_size: 65536 # Ingress buffer size for data
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ep1:
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ctrl: False
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data: True
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buff_size: 0
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ep2:
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ctrl: False
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data: True
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buff_size: 65536
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ep3:
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ctrl: False
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data: True
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buff_size: 0
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ep4:
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ctrl: False
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data: True
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buff_size: 4096
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ep5:
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ctrl: False
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data: True
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buff_size: 4096
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# A list of all NoC blocks in design
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# ----------------------------------
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noc_blocks:
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duc0: # NoC block name
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block_desc: 'duc.yml' # Block device descriptor file
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parameters:
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NUM_PORTS: 1
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ddc0:
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block_desc: 'ddc.yml'
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parameters:
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NUM_PORTS: 2
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radio0:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 2
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duc1:
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block_desc: 'duc.yml'
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parameters:
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NUM_PORTS: 1
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ddc1:
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block_desc: 'ddc.yml'
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parameters:
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NUM_PORTS: 2
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radio1:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 2
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replay0:
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block_desc: 'replay.yml'
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parameters:
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NUM_PORTS: 2
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MEM_DATA_W: 64
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MEM_ADDR_W: 30
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# A list of all static connections in design
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# ------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect
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# - srcport = Port on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Port on the destination block to connect
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connections:
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# RF A TX
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- { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
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- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
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# RF A RX
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- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
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- { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
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# RF A RX2
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- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
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- { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
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#
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# RF B TX
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- { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 }
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- { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
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# RF B RX
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- { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
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- { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 }
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# RF B RX2
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- { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
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- { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
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#
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# Replay Connections
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- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
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- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
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- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
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- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
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#
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# BSP Connections
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- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
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- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
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- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
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- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
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- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
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- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
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- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
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# A list of all clock domain connections in design
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# ------------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect (Always "_device"_)
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# - srcport = Clock domain on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Clock domain on the destination block to connect
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clk_domains:
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- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
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- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
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- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
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- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
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- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
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- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
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- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
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