330 lines
16 KiB
Makefile
330 lines
16 KiB
Makefile
#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
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##-------------------
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##USRP X4xx FPGA Help
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##-------------------
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##Usage:
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## make <Targets> <Options>
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##
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##Output:
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## build/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
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## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file
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## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
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# Base output directory for all builds
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BUILD_BASE_DIR ?= .
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# Definitions
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# MGT Types from x4xx_mgt_type.vh
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MGT_100GbE = 5
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MGT_Aurora = 3
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MGT_10GbE = 2
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MGT_Disabled = 0
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# For a 4-lane MGT like 100GBE set QSFPx_0=MGT_100GbE and all others to
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# MGT_Disabled. For a 1-lane MGT like 10GbE do not set anything for unused
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# lanes. This ensures something is defined only for the lanes that are used, so
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# that the TX/RX signals are connected. The presence of a define causes TX/RX
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# to be declared, whereas declaring TX/RX on an unused lane will cause an error
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# in bitgen for unconstrained pins after it is optimized out.
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QSFP0_10GBE = QSFP0_0=$(MGT_10GbE)
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QSFP0_4X10GBE = QSFP0_0=$(MGT_10GbE) QSFP0_1=$(MGT_10GbE) QSFP0_2=$(MGT_10GbE) QSFP0_3=$(MGT_10GbE)
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QSFP0_100GBE = QSFP0_0=$(MGT_100GbE) QSFP0_1=$(MGT_Disabled) QSFP0_2=$(MGT_Disabled) QSFP0_3=$(MGT_Disabled)
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QSFP1_10GBE = QSFP1_0=$(MGT_10GbE)
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QSFP1_4X10GBE = QSFP1_0=$(MGT_10GbE) QSFP1_1=$(MGT_10GbE) QSFP1_2=$(MGT_10GbE) QSFP1_3=$(MGT_10GbE)
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QSFP1_100GBE = QSFP1_0=$(MGT_100GbE) QSFP1_1=$(MGT_Disabled) QSFP1_2=$(MGT_Disabled) QSFP1_3=$(MGT_Disabled)
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# Target specific variables
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X410_IP: DEFS += $(QSFP0_10GBE) RF_BW=100
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X410_X1_100: DEFS += $(QSFP0_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4_100: DEFS += $(QSFP0_4X10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=0
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X410_C1_100: DEFS += $(QSFP0_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_UC_100: DEFS += $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_C1_200: DEFS += $(QSFP0_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_UC_200: DEFS += $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_CG_200: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X1_200: DEFS += $(QSFP0_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4_200: DEFS += $(QSFP0_4X10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=0
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X410_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_XG_400: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
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X410_UC_400: DEFS += $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
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X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
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X440_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=8*$(DRAM) DRAM_W=128
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X440_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=8*$(DRAM) DRAM_W=128
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X440_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=0
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X440_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=0
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X440_X1_1600: DEFS += $(QSFP0_10GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=2*$(DRAM) DRAM_W=512
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X440_X4_1600: DEFS += $(QSFP0_4X10GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=2*$(DRAM) DRAM_W=512
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X440_C1_1600: DEFS += $(QSFP0_100GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=0
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X440_CG_1600: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=0
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# DRAM IP inclusion. Set to 1 to include DRAM memory controller in design, 0 to
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# exclude it. Note that some targets exclude it regardless of this setting.
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DRAM ?= 1
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DEFS += $(OPTIONS)
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# Initialize a build seed. This can be changed to randomly affect build results.
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BUILD_SEED ?= 0
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DEFS += BUILD_SEED=$(BUILD_SEED)
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# Defaults specific to the various targets:
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X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
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X410_X4C_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_x4c_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_x4c_200_static_router.hex)
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X410_CG_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_cg_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_cg_200_static_router.hex)
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X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
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X410_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_d_static_router.hex)
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X440_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_static_router.hex)
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X440_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_d_static_router.hex)
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X440_1600_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_1600_static_router.hex)
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X440_1600_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_1600_d_static_router.hex)
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# Option to stop after RTL elaboration. Use this flag as a synthesis check.
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ifndef TARGET
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ifdef CHECK
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TARGET = rtl
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else ifdef SYNTH
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TARGET = synth
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else
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TARGET = bin
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endif
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endif
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TOP ?= x4xx
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# vivado_build($1=Device, $2=Definitions, $3=Defaults)
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vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
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vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
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# vivado_build($1=Device, $2=Option)
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ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p build; \
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echo "Exporting bitstream file..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x4xx.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
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echo "Exporting build report..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
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echo "Build DONE ... $(1)_$(2)";
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else
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post_build = @echo "Skipping bitfile export."
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endif
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##
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##Available Targets
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##-------------|-----------|----|-----------------|-----------------|------------
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##Target | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM
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##-------------|-----------|----|-----------------|-----------------|------------
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##X410_X1_100 | 100 MHz | 4 | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
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##X410_XG_100 | 100 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
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##X410_X4_100 | 100 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch
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##X410_X4C_100 | 100 MHz | 4 | 4 x 10 GbE | 100 GbE | Unused
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##X410_C1_100 | 100 MHz | 4 | 100 GbE | Unused | 64b x 4 Ch
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##X410_UC_100 | 100 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch
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##X410_X1_200 | 200 MHz | 4 | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
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##X410_XG_200 | 200 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
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##X410_X4_200 | 200 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch
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##X410_X4C_200 | 200 MHz | 4 | 4 x 10 GbE | 100 GbE | Unused
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##X410_C1_200 | 200 MHz | 4 | 100 GbE | Unused | 64b x 4 Ch
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##X410_UC_200 | 200 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch
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##X410_X1_400 | 400 MHz | 4 | 10 GbE (Lane 0) | Unused | 128b x 4 Ch
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##X410_XG_400 | 400 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 128b x 4 ch
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##X410_X4_400 | 400 MHz | 4 | 4 x 10 GbE | Unused | 128b x 4 Ch
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##X410_C1_400 | 400 MHz | 4 | 100 GbE | Unused | Unused
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##X410_UC_400 | 400 MHz | 4 | Unused | 100 GbE | Unused
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##X410_CG_400 | 400 MHz | 4 | 100 GbE | 100 GbE | Unused
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##X440_X1_400 | 400 MHz | 8 | 10 GbE (Lane 0) | Unused | 128b x 8 Ch
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##X440_X4_400 | 400 MHz | 8 | 4 x 10 GbE | Unused | 128b x 8 Ch
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##X440_C1_400 | 400 MHz | 8 | 100 GbE | Unused | Unused
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##X440_CG_400 | 400 MHz | 8 | 100 GbE | 100 GbE | Unused
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##X440_X1_1600 | 1.6 GHz | 2 | 10 GbE (Lane 0) | Unused | 512b x 2 Ch
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##X440_X4_1600 | 1.6 GHz | 2 | 4 x 10 GbE | Unused | 512b x 2 Ch
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##X440_C1_1600 | 1.6 GHz | 2 | 100 GbE | Unused | Unused
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##X440_CG_1600 | 1.6 GHz | 2 | 100 GbE | 100 GbE | Unused
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##* Note: Not all targets are shipped with UHD
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##* Note: Some YAML configurations might not use all available DRAM channels.
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X410_X1_100: X410_IP build/usrp_x410_fpga_X1_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,X1_100)
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X410_XG_100: X410_IP build/usrp_x410_fpga_XG_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,XG_100)
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X410_X4_100: X410_IP build/usrp_x410_fpga_X4_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,X4_100)
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X410_X4C_100: X410_IP build/usrp_x410_fpga_X4C_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_X4C_200_DEFAULTS))
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$(call post_build,X410,X4C_100)
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X410_C1_100: X410_IP build/usrp_x410_fpga_C1_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
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$(call post_build,X410,C1_100)
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X410_UC_100: X410_IP build/usrp_x410_fpga_UC_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
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$(call post_build,X410,UC_100)
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X410_X1_200: X410_IP build/usrp_x410_fpga_X1_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,X1_200)
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X410_XG_200: X410_IP build/usrp_x410_fpga_XG_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,XG_200)
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X410_X4_200: X410_IP build/usrp_x410_fpga_X4_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,X4_200)
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X410_X4C_200: X410_IP build/usrp_x410_fpga_X4C_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_X4C_200_DEFAULTS))
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$(call post_build,X410,X4C_200)
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X410_C1_200: X410_IP build/usrp_x410_fpga_C1_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
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$(call post_build,X410,C1_200)
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X410_UC_200: X410_IP build/usrp_x410_fpga_UC_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
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$(call post_build,X410,UC_200)
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X410_X1_400: X410_IP build/usrp_x410_fpga_X1_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
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$(call post_build,X410,X1_400)
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X410_XG_400: X410_IP build/usrp_x410_fpga_XG_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
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$(call post_build,X410,XG_400)
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X410_X4_400: X410_IP build/usrp_x410_fpga_X4_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
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$(call post_build,X410,X4_400)
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X410_C1_400: X410_IP build/usrp_x410_fpga_C1_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call post_build,X410,C1_400)
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X410_UC_400: X410_IP build/usrp_x410_fpga_UC_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call post_build,X410,UC_400)
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X410_CG_400: X410_IP build/usrp_x410_fpga_CG_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call post_build,X410,CG_400)
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X440_X1_400: X440_IP build/usrp_x440_fpga_X1_400.dts
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$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_D_DEFAULTS))
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$(call post_build,X440,X1_400)
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X440_X4_400: X440_IP build/usrp_x440_fpga_X4_400.dts
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$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_D_DEFAULTS))
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$(call post_build,X440,X4_400)
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X440_C1_400: X440_IP build/usrp_x440_fpga_C1_400.dts
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$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_DEFAULTS))
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$(call post_build,X440,C1_400)
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X440_CG_400: X440_IP build/usrp_x440_fpga_CG_400.dts
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$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_DEFAULTS))
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$(call post_build,X440,CG_400)
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X440_X1_1600: X440_IP build/usrp_x440_fpga_X1_1600.dts
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$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_D_DEFAULTS))
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$(call post_build,X440,X1_1600)
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X440_X4_1600: X440_IP build/usrp_x440_fpga_X4_1600.dts
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$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_D_DEFAULTS))
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$(call post_build,X440,X4_1600)
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X440_C1_1600: X440_IP build/usrp_x440_fpga_C1_1600.dts
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$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_DEFAULTS))
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$(call post_build,X440,C1_1600)
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X440_CG_1600: X440_IP build/usrp_x440_fpga_CG_1600.dts
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$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_DEFAULTS))
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$(call post_build,X440,CG_1600)
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##
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##Experimental Targets
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##-------------|-----------|----|-----------------|-----------------|------------
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##Target | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM
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##-------------|-----------|----|-----------------|-----------------|------------
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##X410_CG_200 | 200 | 4 | 100 GbE | 100 GbE | 64b x 4 Ch
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X410_CG_200: X410_IP build/usrp_x410_fpga_CG_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
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$(call post_build,X410,CG_200)
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##
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##Other Make Targets
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##------------------
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.DEFAULT_GOAL := all
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all: X410_X4_200 X410_CG_400 X410_UC_200 X440_X4_400 X440_CG_400 X440_X4_1600 X440_CG_1600 ##(Default targets)
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X410_IP: ##Build IP only.
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+$(call vivado_ip,X410,$(DEFS) X410=1)
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X440_IP: ##Build IP only.
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+$(call vivado_ip,X440,$(DEFS) X440=1)
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build/usrp_x410%.dts: dts/*.dts dts/*.dtsi
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-mkdir -p build
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tools/parse_versions_for_dts.py \
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--input regmap/x410/versioning_regs_regmap_utils.vh \
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--output dts/x410-version-info.dtsi \
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--components fpga,cpld_ifc,db_gpio_ifc,rf_core_100m,rf_core_400m
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${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
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$$(python3 tools/get_dts_input.py --target $@)
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build/usrp_x440%.dts: dts/*.dts dts/*.dtsi
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-mkdir -p build
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tools/parse_versions_for_dts.py \
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--input regmap/x440/versioning_regs_regmap_utils.vh \
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--output dts/x440-version-info.dtsi \
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--components fpga,cpld_ifc,db_gpio_ifc,rf_core_full
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${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
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$$(python3 tools/get_dts_input.py --target $@)
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clean: ##Clean up all target build outputs.
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@echo "Cleaning targets..."
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@rm -rf build-X4*
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@rm -rf build
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cleanall: ##Clean up all target and IP build outputs.
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@echo "Cleaning targets and IP..."
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@rm -rf build-ip
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@rm -rf build-X4*
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@rm -rf build
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help: ##Show this help message.
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@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
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##
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##Supported Options
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##-----------------
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##DRAM=0 Exclude DDR4 memory controller IP from the FPGA build.
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##GUI=1 Launch the build in the Vivado GUI.
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##CHECK=1 Launch the syntax checker instead of building a bitfile.
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##SYNTH=1 Launch the build but stop after synthesis.
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##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
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##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)
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.PHONY: all clean cleanall help
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