Wade Fife
032b9677aa
The NET_CHDR_W parameter tells the transport adapter what CHDR width is used in transport packets, such as Ethernet packets. By default the CHDR width used by the transport and RFNoC core will be the same. The NET_CHDR_W parameter can be used in situations where the RFNoC core expects a CHDR width from the transport adapter that is different from that used over the network. In this situation, the transport adapter will rewrite the CHDR packets so that each side gets the expected CHDR width. Original-commit: a9e49b7c587ef778ee0fe327e8bdcb15e0b0fc95
612 lines
23 KiB
Systemverilog
612 lines
23 KiB
Systemverilog
//
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// Copyright 2020 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: chdr_xport_adapter (Ethernet IPV4)
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//
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// Description: An Xport transport adapter module that does the following:
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// - Exposes a configuration port for mgmt packets to configure the node.
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// (chdr_mgmt_pkt_handler)
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// - Implements a return-address map for packets with metadata other than
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// the CHDR. Additional metadata can be passed as a tuser to this module
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// which will store it in a map indexed by the SrcEPID in a management
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// packet. For all returning packets, the metadata will be looked up in
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// the map and attached as the outgoing tuser. (kv_map)
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// - Implements a loopback path for node-info discovery (axi_switch/axi_mux)
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// - Strip UDP headers and extract mac/ip/udp src addresses
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// - Add UDP header for outgoing ethernet traffic
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//
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// Parameters:
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// - PROTOVER: RFNoC protocol version {8'd<major>, 8'd<minor>}
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// - TBL_SIZE: Log2 of the depth of the routing table
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// - NODE_SUBTYPE: The node subtype to return for a node-info discovery
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// - NODE_INST: The node type to return for a node-info discovery
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// - ALLOW_DISC: Controls if the external transport network should be
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// discoverable by management packets from RFNoC side.
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// - NET_CHDR_W: CHDR width used over the network connection
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//
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// Signals:
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// - device_id : The ID of the device that has instantiated this module
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// - my_* : MAC address, IP address, and UDP port that responds/accepts CHDR traffic
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// - eth_rx : The input CHDR stream from the transport
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// - eth_tx : The output CHDR stream to transport
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// - v2e : The input CHDR stream from the rfnoc infrastructure
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// - e2v : The output CHDR stream to the rfnoc infrastructure
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//
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`include "../xport/rfnoc_xport_types.vh"
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module chdr_xport_adapter #(
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int PREAMBLE_BYTES = 6,
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int MAX_PACKET_BYTES = 2**16,
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logic [15:0] PROTOVER = {8'd1, 8'd0},
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int TBL_SIZE = 6,
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logic [7:0] NODE_SUBTYPE = NODE_SUBTYPE_XPORT_IPV4_CHDR64,
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int NODE_INST = 0,
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bit ALLOW_DISC = 1,
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int NET_CHDR_W = 64
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) (
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// Device info (domain: eth_rx.clk)
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input logic [15:0] device_id,
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// Device addresses (domain: eth_rx.clk)
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input logic [47:0] my_mac,
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input logic [31:0] my_ip,
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input logic [15:0] my_udp_chdr_port,
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// Ethernet (domain: eth_rx.clk)
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AxiStreamIf.slave eth_rx, // tUser={*not used*}
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AxiStreamIf.master eth_tx, // tUser={1'b0,trailing bytes}
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// CHDR (domain: eth_rx.clk)
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AxiStreamIf.slave v2e, // tUser={*not used*}
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AxiStreamIf.master e2v // tUser={*not used*}
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);
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//used to store {udp, ipv4, mac}
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localparam USER_META_W = 96;
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localparam ENET_USER_W = $clog2(eth_rx.DATA_WIDTH/8)+1;
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// ---------------------------------------------------
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// RFNoC Includes
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// ---------------------------------------------------
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`include "../core/rfnoc_chdr_utils.vh"
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`include "../core/rfnoc_chdr_internal_utils.vh"
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`include "eth_constants.vh"
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`include "../../axi4s_sv/axi4s.vh"
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// tUser={None}
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AxiStreamPacketIf #(.DATA_WIDTH(eth_rx.DATA_WIDTH),.TKEEP(0),.TUSER(0),
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.MAX_PACKET_BYTES(MAX_PACKET_BYTES))
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ru1(eth_rx.clk,eth_rx.rst);// Packet handler input
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// tUser={None}
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AxiStreamIf #(.DATA_WIDTH(eth_rx.DATA_WIDTH),.TKEEP(0),.TUSER(0),
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.MAX_PACKET_BYTES(MAX_PACKET_BYTES))
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ru2(eth_rx.clk,eth_rx.rst);// Packet handler input
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// tUser={udp_src_port,ipv4_src_addr,eth_src_addr}
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AxiStreamIf #(.DATA_WIDTH(eth_rx.DATA_WIDTH),.USER_WIDTH(USER_META_W),.TKEEP(0))
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ru3(eth_rx.clk,eth_rx.rst);// Packet handler input
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AxiStreamIf #(.DATA_WIDTH(eth_rx.DATA_WIDTH),.USER_WIDTH(USER_META_W),.TKEEP(0))
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ru4(eth_rx.clk,eth_rx.rst);// Packet handler input
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AxiStreamIf #(.DATA_WIDTH(eth_rx.DATA_WIDTH),.USER_WIDTH(USER_META_W),.TKEEP(0))
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ph(eth_rx.clk,eth_rx.rst);// Packet handler input
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// tUser={udp_src_port,ipv4_src_addr,eth_src_addr}
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AxiStreamIf #(.DATA_WIDTH(eth_rx.DATA_WIDTH),.USER_WIDTH(USER_META_W),.TKEEP(0))
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e2d(eth_rx.clk,eth_rx.rst);// Eth => Demux
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AxiStreamIf #(.DATA_WIDTH(eth_rx.DATA_WIDTH),.USER_WIDTH(USER_META_W),.TKEEP(0))
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e2v_resize(eth_rx.clk,eth_rx.rst);// RX Resize => Management packet handler
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logic [1:0] e2d_tid;
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// tUser={udp_src_port,ipv4_src_addr,eth_src_addr}
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AxiStreamIf #(.DATA_WIDTH(eth_rx.DATA_WIDTH),.USER_WIDTH(USER_META_W),.TKEEP(0))
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e2e(eth_rx.clk,eth_rx.rst);// Eth => Eth (loopback)
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// tUser={udp_dst_port, ipv4_dst_addr, eth_dst_addr}
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AxiStreamIf #(.DATA_WIDTH(eth_rx.DATA_WIDTH),.USER_WIDTH(USER_META_W),.TKEEP(0))
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m2e(eth_rx.clk,eth_rx.rst);// Mux => Eth
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logic m2e_tdest; // 1: Return to src, 0: CHDR input
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// ---------------------------------------------------
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// Strip UDP and grab {udp_src_port_old, ipv4_src_addr_old, eth_src_addr_old}
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// ---------------------------------------------------
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always_comb begin : assign_ru1
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`AXI4S_ASSIGN(ru1,eth_rx)
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end
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// Cached fields
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logic [47:0] eth_src_addr_new, eth_src_addr_old;
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logic [31:0] ipv4_src_addr_new, ipv4_src_addr_old;
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logic [15:0] udp_src_port_new, udp_src_port_old;
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// save the fields
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always_ff @(posedge eth_rx.clk) begin : field_ff
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if (eth_rx.rst) begin
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eth_src_addr_old <= '0;
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ipv4_src_addr_old <= '0;
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udp_src_port_old <= '0;
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end else begin
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eth_src_addr_old <= eth_src_addr_new;
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ipv4_src_addr_old <= ipv4_src_addr_new;
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udp_src_port_old <= udp_src_port_new;
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end
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end
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// get the fields - don't use assign. assign will not activate with changes to eth_rx.
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always_comb begin : get_fields
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eth_src_addr_new = ru1.get_packet_field48(eth_src_addr_old,SRC_MAC_BYTE,.NETWORK_ORDER(1));
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ipv4_src_addr_new = ru1.get_packet_field32(ipv4_src_addr_old,SRC_IP_BYTE,.NETWORK_ORDER(1));
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udp_src_port_new = ru1.get_packet_field16(udp_src_port_old,SRC_PORT_BYTE,.NETWORK_ORDER(1));
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end
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// Strip the udp header
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axi4s_remove_bytes #(.REM_START(0),.REM_END(UDP_END)
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) strip_udp (
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.i(ru1), .o(ru2)
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);
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// start driving the port information
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always_comb begin : assign_ru3
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`AXI4S_ASSIGN(ru3,ru2)
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ru3.tuser = {udp_src_port_old, ipv4_src_addr_old, eth_src_addr_old};
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end
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chdr_trim_payload #(
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.CHDR_W(eth_rx.DATA_WIDTH), .USER_W(USER_META_W)
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) chdr_trim_i (
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.clk(eth_rx.clk), .rst(eth_rx.rst),
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.s_axis_tdata(ru3.tdata), .s_axis_tuser(ru3.tuser),
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.s_axis_tlast(ru3.tlast), .s_axis_tvalid(ru3.tvalid), .s_axis_tready(ru3.tready),
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.m_axis_tdata(ru4.tdata), .m_axis_tuser(ru4.tuser),
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.m_axis_tlast(ru4.tlast), .m_axis_tvalid(ru4.tvalid), .m_axis_tready(ru4.tready)
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);
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// Pay close attention to when ph.tuser switches versus when it is needed!
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always_comb begin : assign_ph
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`AXI4S_ASSIGN(ph,ru4)
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end
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// ---------------------------------------------------
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// Rewrite packets from network to use FPGA CHDR_W
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// ---------------------------------------------------
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if (NET_CHDR_W != eth_rx.DATA_WIDTH) begin : gen_chdr_resize_e2v
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chdr_resize #(
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.I_CHDR_W (NET_CHDR_W),
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.O_CHDR_W (eth_rx.DATA_WIDTH),
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.I_DATA_W (eth_rx.DATA_WIDTH),
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.O_DATA_W (eth_rx.DATA_WIDTH),
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.USER_W (USER_META_W),
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.PIPELINE ("IN")
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) chdr_resize_e2v (
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.clk (eth_rx.clk),
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.rst (eth_rx.rst),
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.i_chdr_tdata (ph.tdata),
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.i_chdr_tuser (ph.tuser),
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.i_chdr_tlast (ph.tlast),
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.i_chdr_tvalid (ph.tvalid),
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.i_chdr_tready (ph.tready),
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.o_chdr_tdata (e2v_resize.tdata),
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.o_chdr_tuser (e2v_resize.tuser),
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.o_chdr_tlast (e2v_resize.tlast),
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.o_chdr_tvalid (e2v_resize.tvalid),
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.o_chdr_tready (e2v_resize.tready)
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);
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end else begin : gen_no_chdr_resize_e2v
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always_comb begin
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`AXI4S_ASSIGN(e2v_resize, ph);
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end
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end
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// ---------------------------------------------------
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// Transport => DEMUX
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// ---------------------------------------------------
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logic op_stb;
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logic [15:0] op_src_epid;
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logic [USER_META_W-1:0] op_data;
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logic lookup_stb, lookup_done_stb, lookup_result_match;
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logic [15:0] lookup_epid;
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logic [USER_META_W-1:0] lookup_result_value;
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logic [47:0] node_info;
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always_comb node_info = chdr_mgmt_build_node_info(
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{ 10'h0, NODE_SUBTYPE},
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NODE_INST, NODE_TYPE_TRANSPORT, device_id);
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chdr_mgmt_pkt_handler #(
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.PROTOVER(PROTOVER), .CHDR_W(eth_rx.DATA_WIDTH), .USER_W(USER_META_W), .MGMT_ONLY(0)
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) mgmt_ep_i (
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.clk(eth_rx.clk), .rst(eth_rx.rst),
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.node_info(node_info),
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//ph in
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.s_axis_chdr_tdata(e2v_resize.tdata), .s_axis_chdr_tlast(e2v_resize.tlast),
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.s_axis_chdr_tvalid(e2v_resize.tvalid), .s_axis_chdr_tready(e2v_resize.tready),
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.s_axis_chdr_tuser(e2v_resize.tuser),
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//e2d out
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.m_axis_chdr_tdata(e2d.tdata), .m_axis_chdr_tlast(e2d.tlast),
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.m_axis_chdr_tdest(/* unused */), .m_axis_chdr_tid(e2d_tid),
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.m_axis_chdr_tvalid(e2d.tvalid), .m_axis_chdr_tready(e2d.tready),
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//unused ctrlport
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.ctrlport_req_wr (/* unused */),
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.ctrlport_req_rd (/* unused */),
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.ctrlport_req_addr (/* unused */),
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.ctrlport_req_data (/* unused */),
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.ctrlport_resp_ack (1'b0 /* unused */),
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.ctrlport_resp_data (32'b0 /* unused */),
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// kv_map lookups
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.op_stb(op_stb),
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.op_dst_epid(/* unused */),
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.op_src_epid(op_src_epid),
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.op_data(op_data)
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);
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// Key/Value map.
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// Stores the destination address information for UDP
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// -- storage is controlled from the chdr_managment_node
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// -- lookup is done on each packet passing out
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kv_map #(
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.KEY_WIDTH(16), .VAL_WIDTH(USER_META_W), .SIZE(TBL_SIZE)
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) kv_map_i (
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.clk(eth_rx.clk), .reset(eth_rx.rst),
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.insert_stb(op_stb), .insert_key(op_src_epid), .insert_val(op_data),
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.insert_busy(/* Time between op_stb > Insertion time */),
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.find_key_stb(lookup_stb), .find_key(lookup_epid),
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.find_res_stb(lookup_done_stb),
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.find_res_match(lookup_result_match), .find_res_val(lookup_result_value),
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.count(/* unused */)
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);
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logic ph_hdr = 1'b1;
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always_ff @(posedge eth_rx.clk) begin
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if (eth_rx.rst)
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ph_hdr <= 1'b1;
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else if (ph.tvalid && ph.tready)
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ph_hdr <= ph.tlast;
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end
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// chdr_mgmt_pkt_handler does not buffer packets and has at least one cycle of delay.
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// The tuser caching logic could be more robust.
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always_ff @(posedge eth_rx.clk) begin
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if (ph.tvalid && ph.tready && ph_hdr)
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e2d.tuser <= ph.tuser;
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end
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// ---------------------------------------------------
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// Optional management filter
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// ---------------------------------------------------
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// tUser={*not used*}
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AxiStreamIf #(.DATA_WIDTH(eth_rx.DATA_WIDTH),.TUSER(0),.TKEEP(0))
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f2m(eth_rx.clk,eth_rx.rst);
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if (ALLOW_DISC) begin : gen_no_mgmt_filter
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// Allow all packets to pass through
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always_comb begin
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f2m.tdata = v2e.tdata;
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f2m.tlast = v2e.tlast;
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f2m.tvalid = v2e.tvalid;
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v2e.tready = f2m.tready;
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end
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end else begin : gen_mgmt_filter
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// Disallow forwarding of management discovery packets from RFNoC to the
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// transport interface for transports that don't support them.
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//vhook_nowarn unused_*
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logic [eth_rx.DATA_WIDTH-1:0] unused_tdata;
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logic unused_tlast, unused_tvalid;
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logic [eth_rx.DATA_WIDTH-1:0] s_header;
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logic dispose_pkt;
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// We identify discovery packets by the fact that they are management
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// packets and that they use the null EPID as the destination.
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always_comb dispose_pkt = (chdr_get_pkt_type(s_header[63:0]) == CHDR_PKT_TYPE_MGMT) &&
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(chdr_get_dst_epid(s_header[63:0]) == NULL_EPID);
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axi_demux #(
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.WIDTH (eth_rx.DATA_WIDTH),
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.SIZE (2),
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.PRE_FIFO_SIZE (0),
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.POST_FIFO_SIZE (1)
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) axi_demux_mgmt_filter_i (
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.clk (eth_rx.clk),
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.reset (eth_rx.rst),
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.clear (1'b0),
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.header (s_header),
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.dest (dispose_pkt),
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.i_tdata (v2e.tdata),
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.i_tlast (v2e.tlast),
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.i_tvalid (v2e.tvalid),
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.i_tready (v2e.tready),
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.o_tdata ({unused_tdata, f2m.tdata}),
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.o_tlast ({unused_tlast, f2m.tlast}),
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.o_tvalid ({unused_tvalid, f2m.tvalid}),
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.o_tready ({1'b1, f2m.tready})
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);
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end
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// ---------------------------------------------------
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// MUX and DEMUX for return path
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// ---------------------------------------------------
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logic [USER_META_W-1:0] unused_tuser;
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axis_switch #(
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.DATA_W(eth_rx.DATA_WIDTH+USER_META_W), .DEST_W(1), .IN_PORTS(1), .OUT_PORTS(2), .PIPELINE(0)
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) rtn_demux_i (
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.clk(eth_rx.clk), .reset(eth_rx.rst),
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.s_axis_tdata({e2d.tuser, e2d.tdata}), .s_axis_alloc(1'b0),
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.s_axis_tdest(e2d_tid == CHDR_MGMT_RETURN_TO_SRC ? 2'b01 : 2'b00),
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.s_axis_tlast(e2d.tlast), .s_axis_tvalid(e2d.tvalid), .s_axis_tready(e2d.tready),
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.m_axis_tdata({e2e.tuser, e2e.tdata, unused_tuser, e2v.tdata}),
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.m_axis_tdest(/* unused */),
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.m_axis_tlast({e2e.tlast, e2v.tlast}),
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.m_axis_tvalid({e2e.tvalid, e2v.tvalid}),
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.m_axis_tready({e2e.tready, e2v.tready})
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);
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axi_mux #(
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.WIDTH(eth_rx.DATA_WIDTH+USER_META_W+1), .SIZE(2), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(0)
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) rtn_mux_i (
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.clk(eth_rx.clk), .reset(eth_rx.rst), .clear(1'b0),
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.i_tdata({1'b1, e2e.tuser, e2e.tdata, 1'b0, {USER_META_W{1'b0}}, f2m.tdata}),
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.i_tlast({e2e.tlast, f2m.tlast}),
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.i_tvalid({e2e.tvalid, f2m.tvalid}), .i_tready({e2e.tready, f2m.tready}),
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.o_tdata({m2e_tdest, m2e.tuser, m2e.tdata}), .o_tlast(m2e.tlast),
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.o_tvalid(m2e.tvalid), .o_tready(m2e.tready)
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);
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// ---------------------------------------------------
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// MUX => Transport
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// ---------------------------------------------------
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// In this section we must determine what value to put in tuser. If tdest is
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// 1 then tuser is passed through unchanged. If tdest is 0 then the tuser
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// value is looked up in the KV map using the EPID in the packet header.
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//
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// To do this we split the data (tdata, tlast) and the routing information
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// (tdest, tuser, and the EPID) into two FIFOs. This allows us to perform a
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// routing lookup and decide what to do while we continue to buffer data.
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//
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// With small packets, multiple routing lookups might be enqueued in the
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// lookup_fifo, but we can only do one lookup at a time. Output logic
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// controls release of packets from the data FIFO to ensure we only output
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// one packet per lookup after the lookup is complete.
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AxiStreamIf #(.DATA_WIDTH(eth_rx.DATA_WIDTH),.TUSER(0),.TKEEP(0))
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resize_v2e(eth_rx.clk,eth_rx.rst);
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AxiStreamIf #(.DATA_WIDTH(eth_rx.DATA_WIDTH),.USER_WIDTH(0),.TKEEP(0))
|
|
data_fifo_o(eth_rx.clk,eth_rx.rst);// TX Resize => Management packet handler
|
|
AxiStreamIf #(.DATA_WIDTH(eth_rx.DATA_WIDTH),.TUSER(0),.TKEEP(0))
|
|
data_fifo_i(eth_rx.clk,eth_rx.rst);
|
|
|
|
AxiStreamIf #(.DATA_WIDTH(1+USER_META_W+16),.TUSER(0),.TKEEP(0))
|
|
lookup_fifo_o(eth_rx.clk,eth_rx.rst);
|
|
AxiStreamIf #(.DATA_WIDTH(1+USER_META_W+16),.TUSER(0),.TKEEP(0))
|
|
lookup_fifo_i(eth_rx.clk,eth_rx.rst);
|
|
|
|
logic lookup_fifo_tdest;
|
|
logic [USER_META_W-1:0] lookup_fifo_tuser;
|
|
logic [ 15:0] lookup_fifo_tepid;
|
|
logic non_lookup_done_stb;
|
|
logic resize_v2e_hdr = 1'b1;
|
|
logic pass_packet;
|
|
logic [USER_META_W-1:0] result_tuser;
|
|
logic result_tuser_valid;
|
|
logic [USER_META_W-1:0] reg_o_tuser;
|
|
|
|
// Track when the next m2e word contains is the start of a new packet
|
|
logic m2e_hdr = 1'b1;
|
|
always_ff @(posedge eth_rx.clk) begin : m2e_hdr_ff
|
|
if (eth_rx.rst)
|
|
m2e_hdr <= 1'b1;
|
|
else if (m2e.tvalid && m2e.tready)
|
|
m2e_hdr <= m2e.tlast;
|
|
end
|
|
|
|
// We can only accept data from the mux when when both the data_fifo and
|
|
// lookup_fifo are ready.
|
|
always_comb data_fifo_i.tdata = m2e.tdata;
|
|
always_comb data_fifo_i.tlast = m2e.tlast;
|
|
always_comb data_fifo_i.tvalid = m2e.tvalid && m2e.tready;
|
|
always_comb m2e.tready = data_fifo_i.tready && lookup_fifo_i.tready;
|
|
|
|
// The data_fifo only takes the packet data (tdata, tlast). We use an
|
|
// axi_fifo_short module for the data_fifo because it can tolerate tvalid
|
|
// going low before a transfer completes.
|
|
axi_fifo_short #(
|
|
.WIDTH (1+eth_rx.DATA_WIDTH)
|
|
) data_fifo (
|
|
.clk (eth_rx.clk),
|
|
.reset (eth_rx.rst),
|
|
.clear (1'b0),
|
|
.i_tdata ({data_fifo_i.tlast, data_fifo_i.tdata}),
|
|
.i_tvalid (data_fifo_i.tvalid),
|
|
.i_tready (data_fifo_i.tready),
|
|
.o_tdata ({data_fifo_o.tlast, data_fifo_o.tdata}),
|
|
.o_tvalid (data_fifo_o.tvalid),
|
|
.o_tready (data_fifo_o.tready),
|
|
.space (),
|
|
.occupied ()
|
|
);
|
|
|
|
// ---------------------------------------------------
|
|
// Rewrite packets from FPGA to use network CHDR_W
|
|
// ---------------------------------------------------
|
|
if (NET_CHDR_W != eth_rx.DATA_WIDTH) begin : gen_chdr_resize_v2e
|
|
chdr_resize #(
|
|
.I_CHDR_W (eth_rx.DATA_WIDTH),
|
|
.O_CHDR_W (NET_CHDR_W),
|
|
.I_DATA_W (eth_rx.DATA_WIDTH),
|
|
.O_DATA_W (eth_rx.DATA_WIDTH),
|
|
.USER_W (1),
|
|
.PIPELINE ("OUT")
|
|
) chdr_resize_v2e (
|
|
.clk (eth_rx.clk),
|
|
.rst (eth_rx.rst),
|
|
.i_chdr_tdata (data_fifo_o.tdata),
|
|
.i_chdr_tuser (1'b0),
|
|
.i_chdr_tlast (data_fifo_o.tlast),
|
|
.i_chdr_tvalid (data_fifo_o.tvalid),
|
|
.i_chdr_tready (data_fifo_o.tready),
|
|
.o_chdr_tdata (resize_v2e.tdata),
|
|
.o_chdr_tuser (),
|
|
.o_chdr_tlast (resize_v2e.tlast),
|
|
.o_chdr_tvalid (resize_v2e.tvalid),
|
|
.o_chdr_tready (resize_v2e.tready)
|
|
);
|
|
end else begin : gen_no_chdr_resize_v2e
|
|
always_comb begin
|
|
`AXI4S_ASSIGN(resize_v2e, data_fifo_o);
|
|
end
|
|
end
|
|
|
|
// The lookup FIFO only takes the header routing info (tdest, tuser, epid).
|
|
// We use axi_fifo_short since it can tolerate tvalid going low before a
|
|
// transfer completes.
|
|
|
|
always_comb lookup_fifo_i.tdata = {m2e_tdest, m2e.tuser, chdr_get_dst_epid(m2e.tdata[63:0])};
|
|
always_comb {lookup_fifo_tdest, lookup_fifo_tuser, lookup_fifo_tepid} = lookup_fifo_o.tdata;
|
|
always_comb lookup_fifo_i.tvalid = m2e.tvalid && m2e.tready && m2e_hdr;
|
|
|
|
axi_fifo_short #(
|
|
.WIDTH (1+USER_META_W+16)
|
|
) lookup_fifo (
|
|
.clk (eth_rx.clk),
|
|
.reset (eth_rx.rst),
|
|
.clear (1'b0),
|
|
.i_tdata (lookup_fifo_i.tdata),
|
|
.i_tvalid (lookup_fifo_i.tvalid),
|
|
.i_tready (lookup_fifo_i.tready),
|
|
.o_tdata (lookup_fifo_o.tdata),
|
|
.o_tvalid (lookup_fifo_o.tvalid),
|
|
.o_tready (lookup_fifo_o.tready),
|
|
.space (),
|
|
.occupied ()
|
|
);
|
|
|
|
// Keep track of when we are busy doing a lookup in the KV map.
|
|
logic lookup_busy = 1'b0;
|
|
always_ff @(posedge eth_rx.clk) begin : lookup_busy_ff
|
|
if (eth_rx.rst)
|
|
lookup_busy <= 1'b0;
|
|
else begin
|
|
if (lookup_stb)
|
|
lookup_busy <= 1'b1;
|
|
else if (lookup_done_stb)
|
|
lookup_busy <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// Determine if we can use the output of the lookup_fifo to do a KV map
|
|
// lookup. We only perform a KV map lookup if tdest is 0 and we can only do
|
|
// so if the KV map is free and the holding register for the tuser value is
|
|
// available.
|
|
always_comb lookup_epid = lookup_fifo_tepid;
|
|
always_comb lookup_stb = lookup_fifo_o.tvalid && !lookup_busy &&
|
|
!lookup_fifo_tdest && !result_tuser_valid;
|
|
|
|
// Determine if we can use the output of the lookup FIFO directly (no lookup
|
|
// is needed). We can only use it if we're not already doing a KV lookup and
|
|
// if the holding register for the tuser value is available.
|
|
always_comb non_lookup_done_stb = lookup_fifo_o.tvalid && !lookup_busy &&
|
|
lookup_fifo_tdest && !result_tuser_valid;
|
|
|
|
// Pop the routing info off of the lookup_fifo if we've started its lookup
|
|
always_comb lookup_fifo_o.tready = lookup_stb || non_lookup_done_stb;
|
|
|
|
// Track when the next resize_v2e word is the start of a new packet
|
|
always_ff @(posedge eth_rx.clk) begin : resize_v2e_hdr_ff
|
|
if (eth_rx.rst)
|
|
resize_v2e_hdr <= 1'b1;
|
|
else if (resize_v2e.tvalid && resize_v2e.tready && pass_packet)
|
|
resize_v2e_hdr <= resize_v2e.tlast;
|
|
end
|
|
|
|
// Store the lookup result in a holding register. This can come from the KV
|
|
// map or the incoming tuser.
|
|
always_ff @(posedge eth_rx.clk) begin : result_tuser_ff
|
|
if (eth_rx.rst) begin
|
|
result_tuser <= {USER_META_W{1'bX}}; // Don't care
|
|
result_tuser_valid <= 1'b0;
|
|
end else begin
|
|
// The tuser holding register becomes available as soon as we start
|
|
// transmitting the corresponding packet.
|
|
if (resize_v2e.tvalid && resize_v2e.tready && resize_v2e_hdr && pass_packet) begin
|
|
result_tuser_valid <= 1'b0;
|
|
end
|
|
|
|
// Load the result of the lookup
|
|
if (lookup_done_stb) begin
|
|
result_tuser <= lookup_result_match ? lookup_result_value : {USER_META_W{1'b0}};
|
|
result_tuser_valid <= 1'b1;
|
|
end else if (non_lookup_done_stb) begin
|
|
result_tuser <= lookup_fifo_tuser;
|
|
result_tuser_valid <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
// Control when the packet from the data_fifo can be passed through. Put the
|
|
// tuser value into a register for the duration of the packet.
|
|
always_ff @(posedge eth_rx.clk) begin : pass_packet_ff
|
|
if (eth_rx.rst) begin
|
|
pass_packet <= 1'b0;
|
|
reg_o_tuser <= {USER_META_W{1'bX}}; // Don't care
|
|
end else begin
|
|
// We're done passing through a packet when tlast goes out
|
|
if (resize_v2e.tvalid && resize_v2e.tready && resize_v2e.tlast && pass_packet) begin
|
|
pass_packet <= 1'b0;
|
|
end
|
|
|
|
// We can pass the next packet through when we're at the start of a
|
|
// packet and we have the tuser value waiting in the holding register.
|
|
if (resize_v2e_hdr && result_tuser_valid && !pass_packet) begin
|
|
reg_o_tuser <= result_tuser;
|
|
pass_packet <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
// Device addresses
|
|
logic [15:0] au_udp_dst;
|
|
logic [31:0] au_ip_dst;
|
|
logic [47:0] au_mac_dst;
|
|
|
|
AxiStreamIf #(.DATA_WIDTH(eth_rx.DATA_WIDTH),.TKEEP(0),.TUSER(0))
|
|
au(eth_rx.clk,eth_rx.rst);// Add UDP input
|
|
always_comb begin
|
|
{au_udp_dst,au_ip_dst,au_mac_dst} = reg_o_tuser;
|
|
au.tdata = resize_v2e.tdata;
|
|
au.tlast = resize_v2e.tlast;
|
|
au.tvalid = resize_v2e.tvalid & pass_packet;
|
|
resize_v2e.tready = au.tready & pass_packet;
|
|
end
|
|
|
|
// Clock Crossing to the ethernet clock domain
|
|
logic [47:0] e_my_mac;
|
|
logic [31:0] e_my_ip;
|
|
logic [15:0] e_my_udp_chdr_port;
|
|
// crossing clock boundaries.
|
|
// my_mac, my_ip, my_udp_chdr_port must be written
|
|
// prior to traffic, or an inconsistent version will
|
|
// exist for a clock period or 2. This would be better
|
|
// done with a full handshake.
|
|
synchronizer #(.WIDTH(96),.STAGES(1))
|
|
e_info_sync (.clk(eth_rx.clk),.rst(eth_rx.rst),
|
|
.in({my_mac,my_ip,my_udp_chdr_port}),
|
|
.out({e_my_mac,e_my_ip,e_my_udp_chdr_port}));
|
|
|
|
// add the UDP header back on before sending to EthTx
|
|
eth_ipv4_add_udp #(
|
|
.PREAMBLE_BYTES(PREAMBLE_BYTES),
|
|
.MAX_PACKET_BYTES(MAX_PACKET_BYTES)
|
|
) add_udp_i (
|
|
.i(au), .o(eth_tx),
|
|
.mac_src(e_my_mac),
|
|
.ip_src(e_my_ip),
|
|
.udp_src(e_my_udp_chdr_port),
|
|
.mac_dst(au_mac_dst),
|
|
.ip_dst(au_ip_dst),
|
|
.udp_dst(au_udp_dst)
|
|
);
|
|
|
|
|
|
endmodule : chdr_xport_adapter
|