Wade Fife
f3085587fd
There were some rare corner cases where the EOB could get lost in the DUC due to the dds_timed logic not always passing it through as it should. This resulted in an underflow error message at the end of transmission. This commit also fixes an issue where part of the last packet used a frequency shift of 0 instead of the requested frequency shift, and an issue where the first few samples of a burst used the wrong frequency shift value. Part of the fix includes adding a TUSER port to dds_sin_cos_lut_only. The TUSER port is built into the IP but was disabled. It is now enabled and set to 1 bit wide. This has a very small effect on resource usage and can be left unconnected when not needed. The dds_freq_tune block was shared by the DUC and DDC. To avoid affecting the DDC, a new version, dds_freq_tune_duc, is being added for the DUC to use that has the necessary fixes. The new dds_wrapper.v is a wrapper for the dds_sin_cos_lut_only IP. This IP has the undesirable behavior that new inputs must be provided to push previous outputs through the IP. This wrapper hides that complexity by adding some logic to ensure all data gets pushed through automatically. This logic uses the TUSER port on the IP. Finally, a testbench for dds_timed was added. Original-commit: 77975d108a704ce18ec52b4ee1764381b1893752
69 lines
2.1 KiB
Makefile
69 lines
2.1 KiB
Makefile
#
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# Copyright 2021 Ettus Research, A National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/rfnoc/Makefile.srcs
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DESIGN_SRCS += $(abspath \
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$(RFNOC_SRCS) \
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)
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#-------------------------------------------------
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# IP Specific
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#-------------------------------------------------
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# If simulation contains IP, define the IP_DIR and point
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# it to the base level IP directory.
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IP_DIR = $(BASE_DIR)/x300/ip
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# Include makefiles and sources for all IP components
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# *after* defining the IP_DIR
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include $(LIB_IP_DIR)/complex_multiplier_dds/Makefile.inc
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include $(LIB_IP_DIR)/dds_sin_cos_lut_only/Makefile.inc
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DESIGN_SRCS += $(abspath \
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$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) \
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$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) \
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)
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#-------------------------------------------------
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# ModelSim Specific
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#-------------------------------------------------
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modelsim vlint : DESIGN_SRCS += $(abspath \
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$(IP_BUILD_DIR)/dds_sin_cos_lut_only/sim/dds_sin_cos_lut_only.vhd \
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$(IP_BUILD_DIR)/complex_multiplier_dds/sim/complex_multiplier_dds.vhd \
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)
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MODELSIM_ARGS = glbl
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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SIM_TOP ?= dds_timed_tb
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SIM_SRCS = \
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$(abspath $(SIM_TOP).sv) \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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