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c847bec9e1a035ebcb33dc1d44d63789d5195afc
b210-k7-fpga/lib/control
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Wade Fife c847bec9e1 fpga: lib: Fix indentation in setting_reg.v 
Original-commit: a7050773f206f55de99f36a742df628398e0aae1
2023-01-10 14:18:59 -08:00
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map
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ad5662_auto_spi.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
arb_qualify_master.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_crossbar_intf.sv
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_crossbar_regport.v
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2020-01-28 09:35:36 -08:00
axi_crossbar.v
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2020-01-28 09:35:36 -08:00
axi_fifo_header.v
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2020-01-28 09:35:36 -08:00
axi_forwarding_cam.v
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2020-01-28 09:35:36 -08:00
axi_setting_reg.v
fpga: rfnoc: Add Signal Generator RFNoC block
2020-07-30 12:51:41 -05:00
axi_slave_mux.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_test_vfifo.v
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2020-01-28 09:35:36 -08:00
axil_ctrlport_master.v
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2020-01-28 09:35:36 -08:00
axil_regport_master.v
fpga: lib: Fix writes in axil_regport_master
2020-06-04 11:53:10 -05:00
axil_to_ni_regport.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
bin2gray.v
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2020-01-28 09:35:36 -08:00
binary_encoder.v
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2020-01-28 09:35:36 -08:00
ctrlport_to_regport.v
fpga: lib: Add ctrlport_to_regport bridge
2020-08-19 12:28:22 -05:00
db_control.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
fe_control.v
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2020-01-28 09:35:36 -08:00
filter_bad_sid.v
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2020-01-28 09:35:36 -08:00
gearbox_2x1.v
fpga: lib: Add 2 to 1 gearbox module
2021-06-03 11:26:54 -05:00
glitch_free_mux.v
fpga: lib: add glitch free mux module
2020-12-03 09:02:17 -06:00
gpio_atr_io.v
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2020-01-28 09:35:36 -08:00
gpio_atr.v
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2020-01-28 09:35:36 -08:00
gray2bin.v
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2020-01-28 09:35:36 -08:00
handshake.v
fpga: lib: add handshake to replace FIFO for ctrlport CDC
2020-08-13 07:46:14 -05:00
Makefile.srcs
fpga: lib: Add RegPort SystemVerilog interface
2022-08-29 17:01:45 -05:00
mdio_master.v
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2020-01-28 09:35:36 -08:00
por_gen.v
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2020-01-28 09:35:36 -08:00
priority_encoder_one_hot.v
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2020-01-28 09:35:36 -08:00
priority_encoder.v
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2020-01-28 09:35:36 -08:00
pulse_stretch_min.v
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2020-01-28 09:35:36 -08:00
pulse_stretch.v
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2020-01-28 09:35:36 -08:00
pulse_synchronizer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ram_2port_impl.vh
fpga: lib: Update error call for undefined RW mode
2022-07-18 13:58:41 -06:00
ram_2port.v
fpga: lib: Add read-only strategy for port B in 2-port RAM
2022-06-28 16:33:05 -05:00
regport_if.sv
fpga: lib: Add RegPort SystemVerilog interface
2022-08-29 17:01:45 -05:00
regport_resp_mux.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
regport_to_settingsbus.v
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2020-01-28 09:35:36 -08:00
regport_to_xbar_settingsbus.v
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2020-01-28 09:35:36 -08:00
reset_sync.v
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2020-01-28 09:35:36 -08:00
s7_icap_wb.v
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2020-01-28 09:35:36 -08:00
serial_to_settings_tb.v
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2020-01-28 09:35:36 -08:00
serial_to_settings.v
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2020-01-28 09:35:36 -08:00
setting_reg.v
fpga: lib: Fix indentation in setting_reg.v
2023-01-10 14:18:59 -08:00
settings_bus_mux.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
settings_bus_timed_2clk.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
simple_i2c_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
simple_spi_core_64bit.v
fpga: lib: add extended spi core for 64bit
2020-06-17 07:13:20 -05:00
simple_spi_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
synchronizer_impl.v
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2020-01-28 09:35:36 -08:00
synchronizer.v
fpga: lib: Update example constraint in synchronizer
2021-09-13 13:20:37 -05:00
user_settings.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00