Martin Braun
f07af03214
This simplifies image core files by generating a RADIO_NIPC parameter for the X410, X440 and E31x BSP files. The IO port widths for X410 are now dynamically widened based on the NIPC value, which is a function of the RF_BW parameter, and cannot be modified. The radio block can now read the NIPC value from the BSP, and populate its spc parameter dynamically. This avoids having to know the right spc value when writing YAML image core files and reduces redundancy. This also removes the RADIO_NIPC parameter entirely from all the image core files. This parameter was fine, but it was a bit confusing because it referenced a Verilog parameter, which you just had to know was there in the generated Verilog. By referencing the BSP parameter instead, the YAML files (BSP, radio.yml, and image core file) are now self-contained regarding the RADIO_NIPC/spc information. As a minor upside, the input wire widths for X410's and N310's rfnoc_image_core.sv module are now generated with the correct widths, and not, as before, with the worst-case width (and then we assume Vivado will do the right thing). Original-commit: 53b4d7a21018fe7aabf9f774260aefb41297a41b
67 lines
3.0 KiB
YAML
67 lines
3.0 KiB
YAML
# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: >- # Copyright information used in file headers
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Copyright 2023 Ettus Research, a National Instruments Brand
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license: >- # License information used in file headers
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SPDX-License-Identifier: LGPL-3.0-or-later
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version: '1.0' # File version
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chdr_width: 64 # Bit width of the CHDR bus for this image
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device: 'e310' # USRP type
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default_target: 'E310_SG3'
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image_core_name: 'usrp_e310_sg3_fpga' # Name to use for the generated output files.
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# Change image_core_name and default_target in tandem,
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# because we won't generate the correct DTS files otherwise.
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# A list of all stream endpoints in design
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# ----------------------------------------
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stream_endpoints:
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ep0: # Stream endpoint name
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ctrl: True # Endpoint passes control traffic
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data: True # Endpoint passes data traffic
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buff_size: 16384 # Ingress buffer size for data
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ep1:
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ctrl: False
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data: True
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buff_size: 16384
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# A list of all NoC blocks in design
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# ----------------------------------
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noc_blocks:
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radio0: # NoC block name
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block_desc: 'radio.yml' # Block device descriptor
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parameters:
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NUM_PORTS: 2
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# A list of all static connections in design
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# ------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect
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# - srcport = Port on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Port on the destination block to connect
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connections:
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# TX A
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- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
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# RX A
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- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
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# TX B
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- { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
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# RX B
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- { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
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#
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# BSP Connections
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- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport }
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- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
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- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
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# A list of all clock domain connections in design
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# ------------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect (Always "_device"_)
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# - srcport = Clock domain on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Clock domain on the destination block to connect
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clk_domains:
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- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
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