46 lines
1.3 KiB
Systemverilog
46 lines
1.3 KiB
Systemverilog
//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_if_window
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//
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// Description:
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//
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// Copy requests from slave to master interface when s_ctrlport_req_addr is in
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// address range specified by the parameters.
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//
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// Parameters:
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//
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// BASE_ADDRESS : Base address of the window.
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// This will be the first address in the range.
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// WINDOW_SIZE : Size of the address space for the window.
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// Last address in range will be BASE_ADDRESS + WINDOW_SIZE - 1.
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//
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module ctrlport_if_window #(
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int BASE_ADDRESS = 0,
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int WINDOW_SIZE = 32
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) (
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ctrlport_if.slave s_ctrlport,
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ctrlport_if.master m_ctrlport
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);
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always_comb begin
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// Mask write and read flag
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automatic logic address_in_range = (s_ctrlport.req.addr >= BASE_ADDRESS) &&
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(s_ctrlport.req.addr < BASE_ADDRESS + WINDOW_SIZE);
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// initialize master request by slave request
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m_ctrlport.req = s_ctrlport.req;
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// overwrite write and read flag with in range flag
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m_ctrlport.req.wr = s_ctrlport.req.wr && address_in_range;
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m_ctrlport.req.rd = s_ctrlport.req.rd && address_in_range;
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// transfer reponse without change
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s_ctrlport.resp = m_ctrlport.resp;
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end
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endmodule
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