7e59e9516d
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Original-commit: 7015f5ed2d495f3908773b7c7d74864d0cc3871a
39 lines
848 B
VHDL
39 lines
848 B
VHDL
--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: PcieCmi
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--
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-- Description:
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--
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-- This is an automatically generated file.
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-- Do not modify this file directly!
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity PcieCmi is
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generic (
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kSimulation : natural := 0
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);
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port (
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Clk : in std_logic ;
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acReset : in std_logic ;
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cSerialNumber : in std_logic_vector (39 downto 0);
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cBoardIsReady : in std_logic ;
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cCmiReset : out std_logic ;
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cOtherSideDetected : out std_logic ;
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aCblPrsnt_n : in std_logic ;
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aSdaIn : in std_logic ;
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aSdaOut : out std_logic ;
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aSclIn : in std_logic ;
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aSclOut : out std_logic
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);
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end entity PcieCmi;
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architecture rtl of PcieCmi is
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begin
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end architecture rtl;
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