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b210-k7-fpga/lib/rfnoc/utils
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michael-west d6bcab7c8c FPGA: Add time changed pulse to timekeeper 
The time changed signal was removed and is needed to synchronized the
frontend.  This restores the signal.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 27aad17956a063f72f192dde97cbff675b46fada
2023-05-10 14:22:42 -05:00
..
axis_ctrlport_reg.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_convert_down.v
fpga: rfnoc: Add RFNoC CHDR resize module
2021-11-04 11:04:54 -05:00
chdr_convert_up.v
fpga: rfnoc: Add RFNoC CHDR resize module
2021-11-04 11:04:54 -05:00
chdr_pad_packet.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_resize.v
fpga: rfnoc: Add RFNoC CHDR resize module
2021-11-04 11:04:54 -05:00
chdr_strip_header.sv
fpga: rfnoc: Fix inferred latch in chdr_strip_header
2022-11-13 16:47:57 -06:00
chdr_trim_payload.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
context_builder.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
context_handler_sync.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
context_parser.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_clk_cross.v
fpga: lib: add handshake to replace FIFO for ctrlport CDC
2020-08-13 07:46:14 -05:00
ctrlport_combiner.v
fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1
2020-04-01 11:02:16 -05:00
ctrlport_decoder_param.v
fpga: lib: Modify for loop to Verilog 2001 syntax
2020-03-09 13:40:17 -05:00
ctrlport_decoder.v
fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntax
2020-07-10 15:12:55 -05:00
ctrlport_gate.v
fpga: rfnoc: Add gate to dynamically enable control-port interfaces
2020-04-01 11:02:16 -05:00
ctrlport_reg_ro.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_reg_rw.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_resp_combine.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_splitter.v
fpga: utils: Optimize ctrlport_splitter for NUM_SLAVES = 1
2020-05-12 13:46:28 -05:00
ctrlport_terminator.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_timer.v
fpga: lib: Pipeline ctrlport_timer
2021-06-03 11:26:54 -05:00
ctrlport_to_settings_bus.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_window.v
fpga: x400: Connect Radio Blocks to DIO
2022-01-25 10:18:47 -07:00
Makefile.srcs
fpga: lib: Add chdr_strip_header module
2022-08-29 17:01:45 -05:00
noc_shell_generic_ctrlport_pyld_chdr.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
timekeeper.v
FPGA: Add time changed pulse to timekeeper
2023-05-10 14:22:42 -05:00