Martin Braun ec4fab0340 fpga: Remove Python2 support from build system ...

- 2to3 was used to convert the Python scripts, except where the tool
  choked and manual intervention was required
- All references to "python" where replaced with "python3"
- buffer() was replaced by memoryview()


Original-commit: ca68195b5d12c5410cfac8d459a0b0902c4c72c7

2021-01-04 13:28:36 -06:00

..

check_config.json

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

git-hash.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

ise_jtag_program.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

launch_modelsim.sh

fpga: tools: Fix ModelSim return status

2020-06-18 15:26:07 -05:00

launch_vivado.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

launch_vivado.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

launch_vlint.sh

fpga: tools: Highlight suppressible errors from vlint

2020-06-29 13:41:15 -05:00

setupenv_base.sh

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

shared-ip-loc-manage.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_check_syntax.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_gen_ip_makefile.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

viv_gen_part_id.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

viv_generate_bd.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_generate_hls_ip.tcl

fpga: tools: Fix HLS IP build with Cygwin

2020-05-12 13:47:20 -05:00

viv_generate_ip.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_hardware_utils.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_ip_utils.tcl

fpga: tools: Ignore BD layout info for TCL-based BD

2020-03-12 10:33:24 -05:00

viv_ip_xci_editor.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

viv_sim_project.tcl

fpga: tools: Add contents of directories for HDL source

2020-05-26 13:36:55 -05:00

viv_strategies.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_synth.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_utils.tcl

fpga: tools: Add contents of directories for HDL source

2020-05-26 13:36:55 -05:00

xil_bitfile_parser.py

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00