Wade Fife
b8ded164e5
This causes the latest RFNoC protocol version to be used by default and avoids the need to update YAML files every time the RFNoC protocol version gets bumped. Original-commit: 92016a585a5223a9a7678134e318e412875b64c2
105 lines
4.2 KiB
YAML
105 lines
4.2 KiB
YAML
# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: >- # Copyright information used in file headers
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Ettus Research, A National Instruments Brand
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license: >- # License information used in file headers
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SPDX-License-Identifier: LGPL-3.0-or-later
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version: '1.0' # File version
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chdr_width: 64 # Bit width of the CHDR bus for this image
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device: 'e320'
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default_target: 'E320_1G'
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# A list of all stream endpoints in design
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# ----------------------------------------
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stream_endpoints:
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ep0: # Stream endpoint name
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ctrl: True # Endpoint passes control traffic
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data: True # Endpoint passes data traffic
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buff_size: 32768 # Ingress buffer size for data
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ep1:
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ctrl: False
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data: True
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buff_size: 32768
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ep2:
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ctrl: False
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data: True
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buff_size: 8192
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ep3:
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ctrl: False
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data: True
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buff_size: 8192
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# A list of all NoC blocks in design
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# ----------------------------------
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noc_blocks:
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duc0: # NoC block name
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block_desc: 'duc.yml' # Block device descriptor file
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parameters:
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NUM_PORTS: 2
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ddc0:
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block_desc: 'ddc.yml'
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parameters:
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NUM_PORTS: 2
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radio0:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 2
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fifo0:
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block_desc: 'axi_ram_fifo.yml'
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parameters:
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NUM_PORTS: 2
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# These parameters correspond to the memory interface on the E320
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MEM_ADDR_W: 31
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MEM_DATA_W: 64
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MEM_CLK_RATE: "300e6"
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# Create two non-overlapping 32 MB buffers by default
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FIFO_ADDR_BASE: "{31'h02000000, 31'h00000000}"
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FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF}"
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# A list of all static connections in design
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# ------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect
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# - srcport = Port on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Port on the destination block to connect
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connections:
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# RF A TX
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- { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
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- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
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# RF A RX
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- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
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- { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
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# RF B TX
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- { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 }
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- { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 }
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# RF B RX
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- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
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- { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
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#
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# DRAM FIFO Connections
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- { srcblk: ep2, srcport: out0, dstblk: fifo0, dstport: in_0 }
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- { srcblk: fifo0, srcport: out_0, dstblk: ep2, dstport: in0 }
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- { srcblk: ep3, srcport: out0, dstblk: fifo0, dstport: in_1 }
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- { srcblk: fifo0, srcport: out_1, dstblk: ep3, dstport: in0 }
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#
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# BSP Connections
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- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport }
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- { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram }
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- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
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- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
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# A list of all clock domain connections in design
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# ------------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect (Always "_device"_)
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# - srcport = Clock domain on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Clock domain on the destination block to connect
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clk_domains:
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- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
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- { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc0, dstport: ce }
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- { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc0, dstport: ce }
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- { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem }
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