michael-west
b8163da1d1
The FIR filter applied gain. Removing it caused incorrect scaling and signals where every other sample was zero. Also parameterized heterodyne frontend processing so it would not use resources in images not requiring it. Signed-off-by: michael-west <michael.west@ettus.com> Original-commit: c27519624ec0f3a44ac1130635a03dafcf2e7f13
83 lines
3.6 KiB
Verilog
83 lines
3.6 KiB
Verilog
//
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// Copyright 2017 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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module n3xx_db_fe_core #(
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// Drive SPI core with input spi_clk instead of ce_clk. This is useful if ce_clk is very slow which
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// would cause spi transactions to take a long time. WARNING: This adds a clock crossing FIFO!
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parameter USE_SPI_CLK = 0,
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parameter [7:0] SR_DB_FE_BASE = 160,
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parameter [7:0] RB_DB_FE_BASE = 16,
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parameter WIDTH = 32,
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parameter NUM_SPI_SEN = 8,
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parameter USE_CORRECTION = 0
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)(
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input clk, input reset,
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// Commands from Radio Core
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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output rb_stb, input [7:0] rb_addr, output [63:0] rb_data,
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// Radio datapath
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input tx_stb, input [WIDTH-1:0] tx_data_in, output [WIDTH-1:0] tx_data_out, input tx_running,
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input rx_stb, input [WIDTH-1:0] rx_data_in, output [WIDTH-1:0] rx_data_out, input rx_running,
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// Frontend / Daughterboard I/O
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input [31:0] misc_ins, output [31:0] misc_outs,
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input [31:0] fp_gpio_in, output [31:0] fp_gpio_out, output [31:0] fp_gpio_ddr, input [31:0] fp_gpio_fab,
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input [31:0] db_gpio_in, output [31:0] db_gpio_out, output [31:0] db_gpio_ddr, input [31:0] db_gpio_fab,
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output [31:0] leds,
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input spi_clk, input spi_rst, output [NUM_SPI_SEN-1:0] sen, output sclk, output mosi, input miso
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);
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localparam [7:0] SR_TX_FE_BASE = SR_DB_FE_BASE + 8'd48;
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localparam [7:0] SR_RX_FE_BASE = SR_DB_FE_BASE + 8'd64;
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db_control #(
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.USE_SPI_CLK(USE_SPI_CLK), .SR_BASE(SR_DB_FE_BASE), .RB_BASE(RB_DB_FE_BASE),
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.NUM_SPI_SEN(NUM_SPI_SEN)
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) db_control_i (
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.clk(clk), .reset(reset),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.rb_stb(rb_stb), .rb_addr(rb_addr), .rb_data(rb_data),
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.run_rx(rx_running), .run_tx(tx_running),
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.misc_ins(misc_ins), .misc_outs(misc_outs),
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.fp_gpio_in(fp_gpio_in), .fp_gpio_out(fp_gpio_out), .fp_gpio_ddr(fp_gpio_ddr), .fp_gpio_fab(fp_gpio_fab),
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.db_gpio_in(db_gpio_in), .db_gpio_out(db_gpio_out), .db_gpio_ddr(db_gpio_ddr), .db_gpio_fab(db_gpio_fab),
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.leds(leds),
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.spi_clk(spi_clk), .spi_rst(spi_rst), .sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso)
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);
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generate
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if (USE_CORRECTION == 1) begin
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tx_frontend_gen3 #(
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.SR_OFFSET_I(SR_TX_FE_BASE + 0), .SR_OFFSET_Q(SR_TX_FE_BASE + 1),.SR_MAG_CORRECTION(SR_TX_FE_BASE + 2),
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.SR_PHASE_CORRECTION(SR_TX_FE_BASE + 3), .SR_MUX(SR_TX_FE_BASE + 4),
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.BYPASS_DC_OFFSET_CORR(0), .BYPASS_IQ_COMP(0),
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.DEVICE("7SERIES")
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) tx_fe_corr_i (
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.clk(clk), .reset(reset),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.tx_stb(tx_stb), .tx_i(tx_data_in[31:16]), .tx_q(tx_data_in[15:0]),
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.dac_stb(), .dac_i(tx_data_out[31:16]), .dac_q(tx_data_out[15:0])
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);
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rx_frontend_gen3 #(
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.SR_MAG_CORRECTION(SR_RX_FE_BASE + 0), .SR_PHASE_CORRECTION(SR_RX_FE_BASE + 1), .SR_OFFSET_I(SR_RX_FE_BASE + 2),
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.SR_OFFSET_Q(SR_RX_FE_BASE + 3), .SR_IQ_MAPPING(SR_RX_FE_BASE + 4), .SR_HET_PHASE_INCR(SR_RX_FE_BASE + 5),
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.BYPASS_DC_OFFSET_CORR(0), .BYPASS_IQ_COMP(0), .BYPASS_HETERODYNE(1),
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.DEVICE("7SERIES")
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) rx_fe_corr_i (
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.clk(clk), .reset(reset), .sync_in(),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.adc_stb(rx_stb), .adc_i(rx_data_in[31:16]), .adc_q(rx_data_in[15:0]),
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.rx_stb(), .rx_i(rx_data_out[31:16]), .rx_q(rx_data_out[15:0])
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);
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end else begin
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//TODO: Flesh out this module
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assign tx_data_out = tx_data_in;
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assign rx_data_out = rx_data_in;
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end
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endgenerate
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endmodule
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