Andrew Moch 8cb9bdd331 fpga: lib: Add AXI4 (full) interface ...

Add a SystemVerilog interface for connecting AXI4 ports, and an
associated header file with helper macros.


Original-commit: 04d29e85b0c0698e3de96b54fd3f6e04eb439f74

2021-06-03 11:26:54 -05:00

..

axi.vh

fpga: lib: Add AXI4 (full) interface

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AxiIf.sv

fpga: lib: Add AXI4 (full) interface

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Makefile.srcs

fpga: lib: Add AXI4 (full) interface

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PkgAxi.sv

fpga: lib: Add AXI4 (full) interface

2021-06-03 11:26:54 -05:00