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b210-k7-fpga/lib/control
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Max Köhler ec70691e84 fpga: lib: add handshake to replace FIFO for ctrlport CDC 
The clock crossing of the ctrlport used FIFOs to transfer requests and responses
between clock domains. This commit adds a handshake based on the pulse
synchronizer to reduce the resource usage for ctrlport clock domain crossing.
Data is stored in a single register while the pulse synchronizer handles the
signaling of valid flags.


Original-commit: 2c2bb3a0b7269dcbd8b5933ce1c0c29ca17f599d
2020-08-13 07:46:14 -05:00
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Merge FPGA repository back into UHD repository
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ad5662_auto_spi.v
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arb_qualify_master.v
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axi_crossbar_intf.sv
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axi_crossbar_regport.v
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axi_crossbar.v
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axi_fifo_header.v
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axi_forwarding_cam.v
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axi_setting_reg.v
fpga: rfnoc: Add Signal Generator RFNoC block
2020-07-30 12:51:41 -05:00
axi_slave_mux.v
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axi_test_vfifo.v
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axil_ctrlport_master.v
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axil_regport_master.v
fpga: lib: Fix writes in axil_regport_master
2020-06-04 11:53:10 -05:00
axil_to_ni_regport.v
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bin2gray.v
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binary_encoder.v
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db_control.v
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fe_control.v
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filter_bad_sid.v
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gpio_atr_io.v
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gpio_atr.v
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gray2bin.v
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handshake.v
fpga: lib: add handshake to replace FIFO for ctrlport CDC
2020-08-13 07:46:14 -05:00
Makefile.srcs
fpga: lib: add handshake to replace FIFO for ctrlport CDC
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mdio_master.v
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por_gen.v
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priority_encoder_one_hot.v
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priority_encoder.v
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pulse_stretch_min.v
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pulse_stretch.v
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pulse_synchronizer.v
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ram_2port_impl.vh
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ram_2port.v
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regport_resp_mux.v
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regport_to_settingsbus.v
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regport_to_xbar_settingsbus.v
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reset_sync.v
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s7_icap_wb.v
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serial_to_settings_tb.v
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serial_to_settings.v
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setting_reg.v
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settings_bus_mux.v
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settings_bus_timed_2clk.v
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simple_i2c_core.v
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simple_spi_core_64bit.v
fpga: lib: add extended spi core for 64bit
2020-06-17 07:13:20 -05:00
simple_spi_core.v
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synchronizer_impl.v
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synchronizer.v
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user_settings.v
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