310 lines
12 KiB
Verilog
310 lines
12 KiB
Verilog
//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: noc_shell_window
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//
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// Description:
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//
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// This is a tool-generated NoC-shell for the window block.
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// See the RFNoC specification for more information about NoC shells.
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//
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// Parameters:
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//
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// THIS_PORTID : Control crossbar port to which this block is connected
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// CHDR_W : AXIS-CHDR data bus width
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// MTU : Maximum transmission unit (i.e., maximum packet size in
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// NUM_PORTS : Number of window module instances to connect
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//
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`default_nettype none
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module noc_shell_window #(
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parameter [9:0] THIS_PORTID = 10'd0,
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parameter CHDR_W = 64,
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parameter [5:0] MTU = 10,
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parameter NUM_PORTS = 1
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) (
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//---------------------
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// Framework Interface
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//---------------------
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// RFNoC Framework Clocks
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input wire rfnoc_chdr_clk,
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input wire rfnoc_ctrl_clk,
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input wire ce_clk,
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// NoC Shell Generated Resets
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output wire rfnoc_chdr_rst,
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output wire rfnoc_ctrl_rst,
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output wire ce_rst,
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// RFNoC Backend Interface
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input wire [511:0] rfnoc_core_config,
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output wire [511:0] rfnoc_core_status,
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// AXIS-CHDR Input Ports (from framework)
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input wire [(0+NUM_PORTS)*CHDR_W-1:0] s_rfnoc_chdr_tdata,
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input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tlast,
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input wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tvalid,
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output wire [(0+NUM_PORTS)-1:0] s_rfnoc_chdr_tready,
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// AXIS-CHDR Output Ports (to framework)
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output wire [(0+NUM_PORTS)*CHDR_W-1:0] m_rfnoc_chdr_tdata,
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output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tlast,
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output wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tvalid,
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input wire [(0+NUM_PORTS)-1:0] m_rfnoc_chdr_tready,
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// AXIS-Ctrl Control Input Port (from framework)
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input wire [31:0] s_rfnoc_ctrl_tdata,
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input wire s_rfnoc_ctrl_tlast,
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input wire s_rfnoc_ctrl_tvalid,
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output wire s_rfnoc_ctrl_tready,
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// AXIS-Ctrl Control Output Port (to framework)
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output wire [31:0] m_rfnoc_ctrl_tdata,
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output wire m_rfnoc_ctrl_tlast,
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output wire m_rfnoc_ctrl_tvalid,
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input wire m_rfnoc_ctrl_tready,
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//---------------------
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// Client Interface
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//---------------------
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// CtrlPort Clock and Reset
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output wire ctrlport_clk,
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output wire ctrlport_rst,
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// CtrlPort Master
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output wire m_ctrlport_req_wr,
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output wire m_ctrlport_req_rd,
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output wire [19:0] m_ctrlport_req_addr,
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output wire [31:0] m_ctrlport_req_data,
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input wire m_ctrlport_resp_ack,
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input wire [31:0] m_ctrlport_resp_data,
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// AXI-Stream Payload Context Clock and Reset
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output wire axis_data_clk,
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output wire axis_data_rst,
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// Payload Stream to User Logic: in
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output wire [NUM_PORTS*32*1-1:0] m_in_payload_tdata,
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output wire [NUM_PORTS*1-1:0] m_in_payload_tkeep,
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output wire [NUM_PORTS-1:0] m_in_payload_tlast,
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output wire [NUM_PORTS-1:0] m_in_payload_tvalid,
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input wire [NUM_PORTS-1:0] m_in_payload_tready,
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// Context Stream to User Logic: in
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output wire [NUM_PORTS*CHDR_W-1:0] m_in_context_tdata,
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output wire [NUM_PORTS*4-1:0] m_in_context_tuser,
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output wire [NUM_PORTS-1:0] m_in_context_tlast,
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output wire [NUM_PORTS-1:0] m_in_context_tvalid,
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input wire [NUM_PORTS-1:0] m_in_context_tready,
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// Payload Stream to User Logic: out
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input wire [NUM_PORTS*32*1-1:0] s_out_payload_tdata,
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input wire [NUM_PORTS*1-1:0] s_out_payload_tkeep,
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input wire [NUM_PORTS-1:0] s_out_payload_tlast,
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input wire [NUM_PORTS-1:0] s_out_payload_tvalid,
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output wire [NUM_PORTS-1:0] s_out_payload_tready,
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// Context Stream to User Logic: out
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input wire [NUM_PORTS*CHDR_W-1:0] s_out_context_tdata,
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input wire [NUM_PORTS*4-1:0] s_out_context_tuser,
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input wire [NUM_PORTS-1:0] s_out_context_tlast,
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input wire [NUM_PORTS-1:0] s_out_context_tvalid,
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output wire [NUM_PORTS-1:0] s_out_context_tready
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);
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//---------------------------------------------------------------------------
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// Backend Interface
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//---------------------------------------------------------------------------
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wire data_i_flush_en;
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wire [31:0] data_i_flush_timeout;
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wire [63:0] data_i_flush_active;
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wire [63:0] data_i_flush_done;
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wire data_o_flush_en;
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wire [31:0] data_o_flush_timeout;
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wire [63:0] data_o_flush_active;
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wire [63:0] data_o_flush_done;
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backend_iface #(
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.NOC_ID (32'hD0530000),
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.NUM_DATA_I (0+NUM_PORTS),
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.NUM_DATA_O (0+NUM_PORTS),
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.CTRL_FIFOSIZE ($clog2(32)),
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.MTU (MTU)
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) backend_iface_i (
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_chdr_rst (rfnoc_chdr_rst),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
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.rfnoc_core_config (rfnoc_core_config),
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.rfnoc_core_status (rfnoc_core_status),
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.data_i_flush_en (data_i_flush_en),
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.data_i_flush_timeout (data_i_flush_timeout),
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.data_i_flush_active (data_i_flush_active),
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.data_i_flush_done (data_i_flush_done),
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.data_o_flush_en (data_o_flush_en),
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.data_o_flush_timeout (data_o_flush_timeout),
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.data_o_flush_active (data_o_flush_active),
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.data_o_flush_done (data_o_flush_done)
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);
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//---------------------------------------------------------------------------
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// Reset Generation
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//---------------------------------------------------------------------------
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wire ce_rst_pulse;
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pulse_synchronizer #(.MODE ("POSEDGE")) pulse_synchronizer_ce (
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.clk_a(rfnoc_chdr_clk), .rst_a(1'b0), .pulse_a (rfnoc_chdr_rst), .busy_a (),
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.clk_b(ce_clk), .pulse_b (ce_rst_pulse)
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);
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pulse_stretch_min #(.LENGTH(32)) pulse_stretch_min_ce (
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.clk(ce_clk), .rst(1'b0),
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.pulse_in(ce_rst_pulse), .pulse_out(ce_rst)
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);
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//---------------------------------------------------------------------------
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// Control Path
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//---------------------------------------------------------------------------
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assign ctrlport_clk = ce_clk;
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assign ctrlport_rst = ce_rst;
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ctrlport_endpoint #(
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.THIS_PORTID (THIS_PORTID),
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.SYNC_CLKS (0),
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.AXIS_CTRL_MST_EN (0),
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.AXIS_CTRL_SLV_EN (1),
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.SLAVE_FIFO_SIZE ($clog2(32))
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) ctrlport_endpoint_i (
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
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.ctrlport_clk (ctrlport_clk),
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.ctrlport_rst (ctrlport_rst),
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.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
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.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
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.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
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.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
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.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
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.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
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.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
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.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
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.m_ctrlport_req_wr (m_ctrlport_req_wr),
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.m_ctrlport_req_rd (m_ctrlport_req_rd),
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.m_ctrlport_req_addr (m_ctrlport_req_addr),
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.m_ctrlport_req_data (m_ctrlport_req_data),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
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.m_ctrlport_resp_status (2'b0),
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.m_ctrlport_resp_data (m_ctrlport_resp_data),
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.s_ctrlport_req_wr (1'b0),
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.s_ctrlport_req_rd (1'b0),
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.s_ctrlport_req_addr (20'b0),
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.s_ctrlport_req_portid (10'b0),
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.s_ctrlport_req_rem_epid (16'b0),
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.s_ctrlport_req_rem_portid (10'b0),
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.s_ctrlport_req_data (32'b0),
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.s_ctrlport_req_byte_en (4'hF),
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.s_ctrlport_req_has_time (1'b0),
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.s_ctrlport_req_time (64'b0),
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.s_ctrlport_resp_ack (),
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.s_ctrlport_resp_status (),
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.s_ctrlport_resp_data ()
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);
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//---------------------------------------------------------------------------
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// Data Path
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//---------------------------------------------------------------------------
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genvar i;
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assign axis_data_clk = ce_clk;
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assign axis_data_rst = ce_rst;
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//---------------------
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// Input Data Paths
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//---------------------
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for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_input_in
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chdr_to_axis_pyld_ctxt #(
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.CHDR_W (CHDR_W),
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.ITEM_W (32),
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.NIPC (1),
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.SYNC_CLKS (0),
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.CONTEXT_FIFO_SIZE ($clog2(2)),
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.PAYLOAD_FIFO_SIZE ($clog2(32)),
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.CONTEXT_PREFETCH_EN (1)
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) chdr_to_axis_pyld_ctxt_in_in (
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.axis_chdr_clk (rfnoc_chdr_clk),
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.axis_chdr_rst (rfnoc_chdr_rst),
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.axis_data_clk (axis_data_clk),
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.axis_data_rst (axis_data_rst),
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.s_axis_chdr_tdata (s_rfnoc_chdr_tdata[((0+i)*CHDR_W)+:CHDR_W]),
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.s_axis_chdr_tlast (s_rfnoc_chdr_tlast[0+i]),
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.s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[0+i]),
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.s_axis_chdr_tready (s_rfnoc_chdr_tready[0+i]),
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.m_axis_payload_tdata (m_in_payload_tdata[(32*1)*i+:(32*1)]),
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.m_axis_payload_tkeep (m_in_payload_tkeep[1*i+:1]),
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.m_axis_payload_tlast (m_in_payload_tlast[i]),
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.m_axis_payload_tvalid (m_in_payload_tvalid[i]),
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.m_axis_payload_tready (m_in_payload_tready[i]),
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.m_axis_context_tdata (m_in_context_tdata[CHDR_W*i+:CHDR_W]),
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.m_axis_context_tuser (m_in_context_tuser[4*i+:4]),
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.m_axis_context_tlast (m_in_context_tlast[i]),
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.m_axis_context_tvalid (m_in_context_tvalid[i]),
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.m_axis_context_tready (m_in_context_tready[i]),
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.flush_en (data_i_flush_en),
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.flush_timeout (data_i_flush_timeout),
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.flush_active (data_i_flush_active[0+i]),
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.flush_done (data_i_flush_done[0+i])
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);
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end
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//---------------------
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// Output Data Paths
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//---------------------
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for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_output_out
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axis_pyld_ctxt_to_chdr #(
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.CHDR_W (CHDR_W),
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.ITEM_W (32),
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.NIPC (1),
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.SYNC_CLKS (0),
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.CONTEXT_FIFO_SIZE ($clog2(2)),
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.PAYLOAD_FIFO_SIZE ($clog2(32)),
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.MTU (MTU),
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.CONTEXT_PREFETCH_EN (1)
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) axis_pyld_ctxt_to_chdr_out_out (
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.axis_chdr_clk (rfnoc_chdr_clk),
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.axis_chdr_rst (rfnoc_chdr_rst),
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.axis_data_clk (axis_data_clk),
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.axis_data_rst (axis_data_rst),
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.m_axis_chdr_tdata (m_rfnoc_chdr_tdata[(0+i)*CHDR_W+:CHDR_W]),
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.m_axis_chdr_tlast (m_rfnoc_chdr_tlast[0+i]),
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.m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[0+i]),
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.m_axis_chdr_tready (m_rfnoc_chdr_tready[0+i]),
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.s_axis_payload_tdata (s_out_payload_tdata[(32*1)*i+:(32*1)]),
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.s_axis_payload_tkeep (s_out_payload_tkeep[1*i+:1]),
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.s_axis_payload_tlast (s_out_payload_tlast[i]),
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.s_axis_payload_tvalid (s_out_payload_tvalid[i]),
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.s_axis_payload_tready (s_out_payload_tready[i]),
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.s_axis_context_tdata (s_out_context_tdata[CHDR_W*i+:CHDR_W]),
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.s_axis_context_tuser (s_out_context_tuser[4*i+:4]),
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.s_axis_context_tlast (s_out_context_tlast[i]),
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.s_axis_context_tvalid (s_out_context_tvalid[i]),
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.s_axis_context_tready (s_out_context_tready[i]),
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.framer_errors (),
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.flush_en (data_o_flush_en),
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.flush_timeout (data_o_flush_timeout),
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.flush_active (data_o_flush_active[0+i]),
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.flush_done (data_o_flush_done[0+i])
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);
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end
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endmodule // noc_shell_window
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`default_nettype wire
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