Wade Fife
2612487d43
Adds a 266.667 MHz compute engine clock and uses it instead of the radio clock for the DDC and DUC. Using a faster clock than the radio allows the DDC and DUC to drain after a stall in the data flow. Original-commit: ff55d406a02cc934a5c238d22c836bea08ade3d1
118 lines
4.7 KiB
YAML
118 lines
4.7 KiB
YAML
# General parameters
|
|
# -----------------------------------------
|
|
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
|
|
copyright: >- # Copyright information used in file headers
|
|
Copyright 2023 Ettus Research, a National Instruments Brand
|
|
license: >- # License information used in file headers
|
|
SPDX-License-Identifier: LGPL-3.0-or-later
|
|
version: '1.0' # File version
|
|
chdr_width: 64 # Bit width of the CHDR bus for this image
|
|
device: 'n320'
|
|
default_target: 'N320_HG'
|
|
|
|
# A list of all stream endpoints in design
|
|
# ----------------------------------------
|
|
stream_endpoints:
|
|
ep0: # Stream endpoint name
|
|
ctrl: True # Endpoint passes control traffic
|
|
data: True # Endpoint passes data traffic
|
|
buff_size: 65536 # Ingress buffer size for data
|
|
ep1:
|
|
ctrl: False
|
|
data: True
|
|
buff_size: 65536
|
|
ep2:
|
|
ctrl: False
|
|
data: True
|
|
buff_size: 4096
|
|
ep3:
|
|
ctrl: False
|
|
data: True
|
|
buff_size: 4096
|
|
|
|
# A list of all NoC blocks in design
|
|
# ----------------------------------
|
|
noc_blocks:
|
|
duc0: # NoC block name
|
|
block_desc: 'duc.yml' # Block device descriptor file
|
|
parameters:
|
|
NUM_PORTS: 1
|
|
ddc0:
|
|
block_desc: 'ddc.yml'
|
|
parameters:
|
|
NUM_PORTS: 1
|
|
radio0:
|
|
block_desc: 'radio.yml'
|
|
parameters:
|
|
NUM_PORTS: 1
|
|
duc1:
|
|
block_desc: 'duc.yml'
|
|
parameters:
|
|
NUM_PORTS: 1
|
|
ddc1:
|
|
block_desc: 'ddc.yml'
|
|
parameters:
|
|
NUM_PORTS: 1
|
|
radio1:
|
|
block_desc: 'radio.yml'
|
|
parameters:
|
|
NUM_PORTS: 1
|
|
replay0:
|
|
block_desc: 'replay.yml'
|
|
parameters:
|
|
NUM_PORTS: 2
|
|
MEM_ADDR_W: 31
|
|
|
|
# A list of all static connections in design
|
|
# ------------------------------------------
|
|
# Format: A list of connection maps (list of key-value pairs) with the following keys
|
|
# - srcblk = Source block to connect
|
|
# - srcport = Port on the source block to connect
|
|
# - dstblk = Destination block to connect
|
|
# - dstport = Port on the destination block to connect
|
|
connections:
|
|
# RF 0 TX
|
|
- { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
|
|
- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
|
|
# RF 0 RX
|
|
- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
|
|
- { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
|
|
#
|
|
# RF 1 TX
|
|
- { srcblk: ep1, srcport: out0, dstblk: duc1, dstport: in_0 }
|
|
- { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
|
|
# RF 1 RX
|
|
- { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
|
|
- { srcblk: ddc1, srcport: out_0, dstblk: ep1, dstport: in0 }
|
|
#
|
|
# Replay Connections
|
|
- { srcblk: ep2, srcport: out0, dstblk: replay0, dstport: in_0 }
|
|
- { srcblk: replay0, srcport: out_0, dstblk: ep2, dstport: in0 }
|
|
- { srcblk: ep3, srcport: out0, dstblk: replay0, dstport: in_1 }
|
|
- { srcblk: replay0, srcport: out_1, dstblk: ep3, dstport: in0 }
|
|
#
|
|
# BSP Connections
|
|
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
|
|
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
|
|
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
|
|
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
|
|
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
|
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
|
|
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
|
|
|
|
# A list of all clock domain connections in design
|
|
# ------------------------------------------------
|
|
# Format: A list of connection maps (list of key-value pairs) with the following keys
|
|
# - srcblk = Source block to connect (Always "_device"_)
|
|
# - srcport = Clock domain on the source block to connect
|
|
# - dstblk = Destination block to connect
|
|
# - dstport = Clock domain on the destination block to connect
|
|
clk_domains:
|
|
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
|
|
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
|
|
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
|
|
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
|
|
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
|
|
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
|
|
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
|