Javier Valenzuela
a6fc53b4e6
The main changes included are: - Variant-dependent pin-out instantiation. - Update clocking scheme in top level file to include XO3 PLL - Add ability to shift outgoing data for the GPIO communication interface with the X410 FPGA. - Include project files required to build the XO3 variant of the ZBX CPLD. - Add build flow for Lattice Diamond designs. - Add ability to build XO3 variant of ZBX CPLD. Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
267 lines
7.9 KiB
Verilog
267 lines
7.9 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: led_control
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//
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// Description:
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// Implements control over LED state via CtrlPort. The default state
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// has the LEDs disabled. Uses RAM to store multiple ATR configurations.
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//
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`default_nettype none
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module led_control #(
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parameter [19:0] BASE_ADDRESS = 0,
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parameter [19:0] SIZE_ADDRESS = 0
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) (
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// Clock and reset
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// Request
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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// Response
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output reg s_ctrlport_resp_ack,
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output reg [ 1:0] s_ctrlport_resp_status = 2'b0,
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output reg [31:0] s_ctrlport_resp_data = 32'b0,
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// LED Control (domain: ctrlport_clk)
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output reg ch0_rx2_led,
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output reg ch0_tx_led,
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output reg ch0_rx_led,
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output reg ch1_rx2_led,
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output reg ch1_tx_led,
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output reg ch1_rx_led,
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// ATR switching
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input wire [ 7:0] atr_config_rf0,
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input wire [ 7:0] atr_config_rf1
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);
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`include "../regmap/led_setup_regmap_utils.vh"
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`include "../../../../../../lib/rfnoc/core/ctrlport.vh"
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//---------------------------------------------------------------
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// ATR memory signals
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//---------------------------------------------------------------
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reg ram_ch0_wea;
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wire [31:0] ram_ch0_doa;
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wire [31:0] ram_ch0_dob;
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reg ram_ch1_wea;
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wire [31:0] ram_ch1_dob;
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//---------------------------------------------------------------
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// Handling of CtrlPort
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//---------------------------------------------------------------
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// Check of request address is targeted for this module.
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wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);
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// Read request shift register to align memory read and response generation.
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reg [ 1:0] read_req_shift_reg = 2'b0;
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// Mask out 8 bits for ATR configurations to be able to compare all ATR
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// configurations against the same base register address.
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wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]};
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// Extract masked out bits from the address, which represent the register
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// array index = ATR configuration index
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wire [ 7:0] register_index = s_ctrlport_req_addr[9:2];
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always @(posedge ctrlport_clk) begin
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// reset internal registers and responses
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if (ctrlport_rst) begin
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s_ctrlport_resp_ack <= 1'b0;
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read_req_shift_reg <= 2'b0;
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ram_ch0_wea <= 1'b0;
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ram_ch1_wea <= 1'b0;
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end else begin
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// default assignments
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read_req_shift_reg <= {read_req_shift_reg[0], s_ctrlport_req_rd};
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ram_ch0_wea <= 1'b0;
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ram_ch1_wea <= 1'b0;
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// write requests
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if (s_ctrlport_req_wr) begin
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// always issue an ack and no data
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_data <= {32{1'bx}};
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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case (register_base_address)
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BASE_ADDRESS + LED_CONTROL(0): begin
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ram_ch0_wea <= 1'b1;
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ram_ch1_wea <= 1'b1;
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end
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// error on undefined address
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default: begin
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// no response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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// Answer read requests delayed by 2 clock cycles. This compensated for
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// register ram_addr and the memory internal address register to make sure
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// ram_ch0_doa is up to date when generating the response.
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end else if (read_req_shift_reg[1]) begin
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// default assumption: valid request
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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s_ctrlport_resp_data <= {32{1'b0}};
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case (register_base_address)
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BASE_ADDRESS + LED_CONTROL(0): begin
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s_ctrlport_resp_data <= ram_ch0_doa & LED_CONTROL_TYPE_MASK;
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end
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// error on undefined address
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default: begin
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// no response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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// no request
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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end
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// register without reset
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reg [ 7:0] ram_addr = 8'b0;
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reg [31:0] ram_datain = 32'b0;
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always @(posedge ctrlport_clk) begin
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// memories
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ram_addr <= register_index;
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ram_datain <= s_ctrlport_req_data;
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//outputs
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ch0_rx2_led <= ram_ch0_dob[CH0_RX2_LED_EN];
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ch0_tx_led <= ram_ch0_dob[CH0_TRX1_LED_EN + 1];
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ch0_rx_led <= ram_ch0_dob[CH0_TRX1_LED_EN + 0];
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ch1_rx2_led <= ram_ch1_dob[CH1_RX2_LED_EN];
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ch1_tx_led <= ram_ch1_dob[CH1_TRX1_LED_EN + 1];
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ch1_rx_led <= ram_ch1_dob[CH1_TRX1_LED_EN + 0];
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end
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`ifdef VARIANT_XO3
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localparam RAM_RW_MODE = "B-READ-ONLY" ;
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`else
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localparam RAM_RW_MODE = "READ-FIRST" ;
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`endif
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ram_2port #(
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.DWIDTH (32),
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.AWIDTH (8),
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.RW_MODE (RAM_RW_MODE),
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.RAM_TYPE ("AUTOMATIC"),
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.OUT_REG (0),
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.INIT_FILE ("")
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) ram_ch0_i (
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.clka (ctrlport_clk),
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.ena (1'b1),
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.wea (ram_ch0_wea),
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.addra (ram_addr),
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.dia (ram_datain),
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.doa (ram_ch0_doa),
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.clkb (ctrlport_clk),
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.enb (1'b1),
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.web (1'b0),
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.addrb (atr_config_rf0),
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.dib (0),
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.dob (ram_ch0_dob)
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);
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ram_2port #(
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.DWIDTH (32),
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.AWIDTH (8),
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.RW_MODE (RAM_RW_MODE),
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.RAM_TYPE ("AUTOMATIC"),
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.OUT_REG (0),
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.INIT_FILE ("")
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) ram_ch1_i (
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.clka (ctrlport_clk),
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.ena (1'b1),
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.wea (ram_ch1_wea),
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.addra (ram_addr),
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.dia (ram_datain),
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.doa (),
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.clkb (ctrlport_clk),
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.enb (1'b1),
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.web (1'b0),
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.addrb (atr_config_rf1),
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.dib (0),
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.dob (ram_ch1_dob));
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endmodule
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`default_nettype wire
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//XmlParse xml_on
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//<regmap name="LED_SETUP_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
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// <group name="LED_SETUP_REGISTERS">
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// <info>
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// Contains registers that control the LEDs.
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// </info>
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// <regtype name="LED_CONTROL_TYPE" size="32" attributes="Readable|Writable">
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// <info>
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// Defines LED functionality.
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// </info>
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// <bitfield name="CH0_RX2_LED_EN" range="0" initialvalue="0">
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// <info>
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// Enables the Ch0 Rx2 Green LED
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// </info>
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// </bitfield>
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// <bitfield name="CH0_TRX1_LED_EN" range="2..1" initialvalue="0">
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// <info>
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// This bitfield controls the RG LED{BR/}
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// Bit 6 controls the Ch0 Rx Green LED{BR/}
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// Bit 7 controls the Ch0 Tx Red LED{BR/}
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// </info>
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// </bitfield>
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// <bitfield name="CH1_RX2_LED_EN" range="16" initialvalue="0">
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// <info>
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// Enables the Ch1 Rx2 Green LED
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// </info>
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// </bitfield>
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// <bitfield name="CH1_TRX1_LED_EN" range="18..17" initialvalue="0">
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// <info>
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// This bitfield controls the RG LED{BR/}
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// Bit 15 controls the Ch1 Rx Green LED{BR/}
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// Bit 14 controls the Ch1 Tx Red LED{BR/}
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// </info>
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// </bitfield>
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// </regtype>
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//
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// <register name="LED_CONTROL" offset="0x0" count="256" step="4" typename="LED_CONTROL_TYPE">
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// <info>
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// This register array can hold settings for all ATR configurations.
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// The register index equals the ATR configuration.
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// The active configuration can be selected in @.ATR_REGMAP.
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// Independently all configurations can be read/written at any time.
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// </info>
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// </register>
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// </group>
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//</regmap>
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//XmlParse xml_off
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