Javier Valenzuela
a6fc53b4e6
The main changes included are: - Variant-dependent pin-out instantiation. - Update clocking scheme in top level file to include XO3 PLL - Add ability to shift outgoing data for the GPIO communication interface with the X410 FPGA. - Include project files required to build the XO3 variant of the ZBX CPLD. - Add build flow for Lattice Diamond designs. - Add ability to build XO3 variant of ZBX CPLD. Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
245 lines
8.1 KiB
Verilog
245 lines
8.1 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: basic_regs
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//
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// Description:
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// Basic Registers to inform software about version and capabilities.
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//
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`default_nettype none
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module basic_regs #(
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parameter [19:0] BASE_ADDRESS = 0,
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parameter [19:0] SIZE_ADDRESS = 0
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) (
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// Request
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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// Response
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output reg s_ctrlport_resp_ack,
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output reg [ 1:0] s_ctrlport_resp_status,
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output reg [31:0] s_ctrlport_resp_data,
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//reg clk domain
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input wire ctrlport_clk,
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input wire ctrlport_rst
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);
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`include "../regmap/basic_regs_regmap_utils.vh"
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`include "../../../../../../lib/rfnoc/core/ctrlport.vh"
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//----------------------------------------------------------
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// Internal registers
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//----------------------------------------------------------
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reg [SCRATCH_REG_SIZE-1:0] scratch_reg = {SCRATCH_REG_SIZE {1'b0}};
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`ifdef VARIANT_XO3
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localparam VARIANT_ID = VARIANT_ID_XO3;
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`else
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localparam VARIANT_ID = VARIANT_ID_MAX10;
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`endif
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//----------------------------------------------------------
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// Handling of CtrlPort
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//----------------------------------------------------------
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wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);
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always @(posedge ctrlport_clk) begin
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// reset internal registers and responses
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if (ctrlport_rst) begin
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scratch_reg <= {SCRATCH_REG_SIZE {1'b0}};
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s_ctrlport_resp_ack <= 1'b0;
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s_ctrlport_resp_data <= {32{1'bx}};
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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end else begin
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// write requests
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if (s_ctrlport_req_wr) begin
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// always issue an ack and no data
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_data <= {32{1'bx}};
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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case (s_ctrlport_req_addr)
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BASE_ADDRESS + SLAVE_SCRATCH: begin
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scratch_reg <= s_ctrlport_req_data[ SCRATCH_REG_MSB : SCRATCH_REG];
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end
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// error on undefined address
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default: begin
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// no response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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// read requests
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end else if (s_ctrlport_req_rd) begin
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// default assumption: valid request
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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s_ctrlport_resp_data <= {32{1'b0}};
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case (s_ctrlport_req_addr)
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BASE_ADDRESS + SLAVE_SIGNATURE: begin
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s_ctrlport_resp_data[BOARD_ID_MSB : BOARD_ID]
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<= BOARD_ID_VALUE[BOARD_ID_SIZE-1:0];
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end
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BASE_ADDRESS + SLAVE_REVISION: begin
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s_ctrlport_resp_data[REVISION_REG_MSB : REVISION_REG]
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<= CPLD_REVISION[REVISION_REG_SIZE-1:0];
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end
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BASE_ADDRESS + SLAVE_OLDEST_REVISION: begin
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s_ctrlport_resp_data[OLDEST_REVISION_REG_MSB : OLDEST_REVISION_REG]
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<= OLDEST_CPLD_REVISION[OLDEST_REVISION_REG_SIZE-1:0];
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end
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BASE_ADDRESS + SLAVE_SCRATCH: begin
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s_ctrlport_resp_data[SCRATCH_REG_MSB : SCRATCH_REG] <= scratch_reg;
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end
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BASE_ADDRESS + GIT_HASH_REGISTER: begin
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`ifdef GIT_HASH
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s_ctrlport_resp_data <= `GIT_HASH;
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`else
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s_ctrlport_resp_data <= 32'hDEADBEEF;
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`endif
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end
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BASE_ADDRESS + SLAVE_VARIANT: begin
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s_ctrlport_resp_data[VARIANT_REG_MSB : VARIANT_REG]
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<= VARIANT_ID[VARIANT_REG_SIZE-1:0];
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end
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// error on undefined address
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default: begin
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s_ctrlport_resp_data <= {32{1'b0}};
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// no response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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// no request
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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end
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endmodule
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`default_nettype wire
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//XmlParse xml_on
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//<regmap name="BASIC_REGS_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
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// <group name="BASIC_REGS_REGISTERS" size="0x010">
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// <info>
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// This regmap contains the revision registers, signature register, a scratch register, and a slave control reg.
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// </info>
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//
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// <enumeratedtype name="BASIC_REGISTERS_VALUES" showhexvalue="true">
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// <info>
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// This enum is used to create the constants held in the basic registers in both verilog and vhdl.
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// </info>
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// <value name="BOARD_ID_VALUE" integer="0x4002"/>
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// <value name="CPLD_REVISION" integer="0x22031611"/>
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// <value name="OLDEST_CPLD_REVISION" integer="0x20110611"/>
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// <value name="VARIANT_ID_XO3" integer="0x584F33"/>
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// <value name="VARIANT_ID_MAX10" integer="0x4D4158"/>
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// </enumeratedtype>
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//
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// <register name="SLAVE_SIGNATURE" size="32" offset="0x00" attributes="Readable">
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// <info>
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// This register contains the unique signature of the DB. This signature is the same value as the one
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// stored on the board ID EEPROM
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// </info>
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// <bitfield name="BOARD_ID" range="15..0" type="integer">
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// <info>
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// Board ID corresponds to the las 16 digits of the daughterboard part number.
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// </info>
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// </bitfield>
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// </register>
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//
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// <register name="SLAVE_REVISION" size="32" offset="0x04" attributes="Readable">
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// <info>
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// This register contains the revision number of the current build
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// </info>
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// <bitfield name="REVISION_REG" range="31..0" type="integer">
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// <info>
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// Returns the revision in YYMMDDHH format
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// </info>
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// </bitfield>
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// </register>
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//
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// <register name="SLAVE_OLDEST_REVISION" size="32" offset="0x08" attributes="Readable">
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// <info>
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// This register contains the revision number of the oldest compatible revision
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// </info>
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// <bitfield name="OLDEST_REVISION_REG" range="31..0" type="integer">
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// <info>
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// Returns the oldest compatible revision in YYMMDDHH format
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// </info>
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// </bitfield>
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// </register>
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//
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// <register name="SLAVE_SCRATCH" size="32" offset="0x0C" attributes="Readable|Writable">
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// <info>
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// Read/write scratch register
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// </info>
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// <bitfield name="SCRATCH_REG" range="31..0" initialvalue="0">
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// <info>
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// Returns the value written here previously.
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// </info>
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// </bitfield>
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// </register>
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//
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// <register name="GIT_HASH_REGISTER" offset="0x10" size="32" writable="false">
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// <info>
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// Git hash of commit used to build this image.{br}
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// Value equals 0xDEADBEEF if the git hash was not used during synthesis.
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// </info>
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// <bitfield name="GIT_CLEAN" range="31..28">
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// <info>
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// 0x0 in case the git status was clean{br}
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// 0xF in case there were uncommitted changes
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// </info>
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// </bitfield>
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// <bitfield name="GIT_HASH" range="27..0">
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// <info>7 hex digit hash code of the commit</info>
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// </bitfield>
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// </register>
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//
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// <register name="SLAVE_VARIANT" size="32" offset="0x14" writable="false">
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// <info>
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// Contains information pertaining the variant of the programmable.
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// </info>
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// <bitfield name="VARIANT_REG" range="31..0" initialvalue="0">
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// <info>
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// Returns the variant of the programmable based on the part vendor.
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// MAX10 variants return 0x583033(ASCII for MAX), while the XO3 variant
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// returns 0x584F33 (ASCII for XO3)
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// </info>
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// </bitfield>
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// </register>
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// </group>
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//</regmap>
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//XmlParse xml_off
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