37 lines
1.4 KiB
Systemverilog
37 lines
1.4 KiB
Systemverilog
//
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// Copyright 2022 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: mb_cpld_pl_regmap_utils.vh
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// Description:
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// The constants in this file are autogenerated by XmlParse.
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//===============================================================================
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// A numerically ordered list of registers and their HDL source files
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//===============================================================================
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// PL_REGISTERS : 0x0 (mb_cpld.v)
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// JTAG_DB0 : 0x60 (mb_cpld.v)
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// JTAG_DB1 : 0x80 (mb_cpld.v)
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//===============================================================================
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// RegTypes
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//===============================================================================
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//===============================================================================
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// Register Group MB_CPLD_PL_WINDOWS
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//===============================================================================
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// PL_REGISTERS Window (from mb_cpld.v)
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localparam PL_REGISTERS = 'h0; // Window Offset
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localparam PL_REGISTERS_SIZE = 'h40; // size in bytes
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// JTAG_DB0 Window (from mb_cpld.v)
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localparam JTAG_DB0 = 'h60; // Window Offset
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localparam JTAG_DB0_SIZE = 'h20; // size in bytes
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// JTAG_DB1 Window (from mb_cpld.v)
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localparam JTAG_DB1 = 'h80; // Window Offset
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localparam JTAG_DB1_SIZE = 'h20; // size in bytes
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