332 lines
12 KiB
Verilog
332 lines
12 KiB
Verilog
//
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// Copyright 2014 Ettus Research LLC
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// Copyright 2018 Ettus Research, a National Instruments Company
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Adapts from internal CHDR to Ethernet packets. Also handles ZPU and Ethernet
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// crossover interfaces.
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//
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`default_nettype none
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module x300_eth_interface #(
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parameter [15:0] PROTOVER = {8'd1, 8'd0},
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parameter MTU = 10,
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parameter NODE_INST = 0,
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parameter RT_TBL_SIZE = 6,
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parameter ETH_BASE = 0,
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parameter TA_BASE = 16,
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parameter [ 0:0] EN_RX_RAW_PYLD = 1,
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parameter [ 0:0] EN_RX_KV_MAP_CFG = 1
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) (
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input wire clk,
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input wire reset,
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// RFNoC Device ID
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input wire [15:0] device_id,
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// Settings bus
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input wire set_stb,
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input wire [ 7:0] set_addr,
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input wire [31:0] set_data,
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input wire [ 7:0] rb_addr,
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output reg [31:0] rb_data,
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// Eth ports
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output wire [63:0] eth_tx_tdata,
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output wire [ 3:0] eth_tx_tuser,
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output wire eth_tx_tlast,
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output wire eth_tx_tvalid,
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input wire eth_tx_tready,
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input wire [63:0] eth_rx_tdata,
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input wire [ 3:0] eth_rx_tuser,
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input wire eth_rx_tlast,
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input wire eth_rx_tvalid,
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output wire eth_rx_tready,
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// CHDR Interface
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output wire [63:0] e2v_tdata,
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output wire e2v_tlast,
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output wire e2v_tvalid,
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input wire e2v_tready,
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input wire [63:0] v2e_tdata,
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input wire v2e_tlast,
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input wire v2e_tvalid,
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output wire v2e_tready,
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// ZPU
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output wire [63:0] e2z_tdata,
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output wire [ 3:0] e2z_tuser,
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output wire e2z_tlast,
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output wire e2z_tvalid,
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input wire e2z_tready,
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input wire [63:0] z2e_tdata,
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input wire [ 3:0] z2e_tuser,
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input wire z2e_tlast,
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input wire z2e_tvalid,
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output wire z2e_tready
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);
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//---------------------------------------------------------------------------
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// Ethernet Registers
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//---------------------------------------------------------------------------
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// UNUSED: ETH_BASE to ETH_BASE+7
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localparam MY_ETH_ADDR_LO_REG = ETH_BASE + 8;
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localparam MY_ETH_ADDR_HI_REG = ETH_BASE + 9;
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localparam MY_IP_ADDR_REG = ETH_BASE + 10;
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localparam MY_UDP_PORT_REG = ETH_BASE + 11;
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// UNUSED: ETH_BASE+12 to ETH_BASE+15
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wire [47:0] my_eth_addr;
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wire [31:0] my_ipv4_addr;
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wire [15:0] my_udp_chdr_port;
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// MAC address for the dispatcher module.
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// This value is used to determine if the packet is meant for this device.
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setting_reg #(.my_addr(MY_ETH_ADDR_LO_REG), .awidth(8), .width(32)) sr_my_mac_lsb
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(my_eth_addr[31:0]),.changed());
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setting_reg #(.my_addr(MY_ETH_ADDR_HI_REG), .awidth(8), .width(16)) sr_my_mac_msb
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(my_eth_addr[47:32]),.changed());
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// IP address for the dispatcher module.
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// This value is used to determine if the packet is addressed
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// to this device.
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setting_reg #(.my_addr(MY_IP_ADDR_REG), .awidth(8), .width(32)) sr_my_ip
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(my_ipv4_addr[31:0]),.changed());
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// This module supports one destination port
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setting_reg #(.my_addr(MY_UDP_PORT_REG), .awidth(8), .width(16)) sr_udp_port
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({my_udp_chdr_port[15:0]}),.changed());
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//---------------------------------------------------------------------------
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// Transport Adapter Registers
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//---------------------------------------------------------------------------
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// See eth_regs for a description of the bit fields.
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localparam [7:0] REG_XPORT_COMPAT = TA_BASE + 0;
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localparam [7:0] REG_XPORT_INFO = TA_BASE + 1;
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localparam [7:0] REG_XPORT_NODE_INST = TA_BASE + 2;
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localparam [7:0] REG_XPORT_KV_MAC_LO = TA_BASE + 3;
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localparam [7:0] REG_XPORT_KV_MAC_HI = TA_BASE + 4;
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localparam [7:0] REG_XPORT_KV_IP = TA_BASE + 5;
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localparam [7:0] REG_XPORT_KV_UDP = TA_BASE + 6;
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localparam [7:0] REG_XPORT_KV_CFG = TA_BASE + 7;
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// Note: TA_BASE + 8 is a virtual register used for ARP (see x300 firmware)
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localparam [7:0] REG_IPV4_ARP = TA_BASE + 8;
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localparam [7:0] COMPAT_MAJOR = 8'd1;
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localparam [7:0] COMPAT_MINOR = 8'd0;
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// KV map configuration registers. Make them default to 0 so that the extra
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// logic for this configuration interface gets optimized out when not used.
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reg kv_stb = 0;
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reg [47:0] kv_mac_addr = 0;
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reg [31:0] kv_ip_addr = 0;
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reg [15:0] kv_udp_port = 0;
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reg [15:0] kv_dst_epid = 0;
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reg kv_raw_udp = 0;
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wire kv_busy;
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if (EN_RX_KV_MAP_CFG) begin : gen_write_regs
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// Implement register writes (settings regs)
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always @(posedge clk) begin : ta_reg_write
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if (reset) begin
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kv_stb <= 0;
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end else begin
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kv_stb <= 0;
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if (set_stb) begin
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case (set_addr)
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REG_XPORT_KV_MAC_LO:
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kv_mac_addr[31:0] <= set_data;
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REG_XPORT_KV_MAC_HI:
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kv_mac_addr[47:32] <= set_data[15:0];
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REG_XPORT_KV_IP:
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kv_ip_addr <= set_data[31:0];
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REG_XPORT_KV_UDP:
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kv_udp_port <= set_data[15:0];
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REG_XPORT_KV_CFG: begin
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kv_dst_epid <= set_data[15:0];
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kv_raw_udp <= set_data[16];
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kv_stb <= 1;
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end
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endcase
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end
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end
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end // ta_reg_write
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end // gen_write_regs
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// Implement register reads (readback regs)
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always @(*) begin : ta_reg_read
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rb_data = 32'd0;
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case (rb_addr)
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REG_XPORT_COMPAT:
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rb_data[15:0] = { COMPAT_MAJOR, COMPAT_MINOR };
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REG_XPORT_INFO:
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rb_data[1:0] = { EN_RX_RAW_PYLD, EN_RX_KV_MAP_CFG };
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REG_XPORT_NODE_INST:
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rb_data = NODE_INST;
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REG_XPORT_KV_CFG:
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if (EN_RX_KV_MAP_CFG) begin
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rb_data[31] = kv_busy;
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end
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default:
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rb_data = 32'd0;
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endcase
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end
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//---------------------------------------------------------------------------
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// Transport Adapter
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//---------------------------------------------------------------------------
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if (EN_RX_KV_MAP_CFG || EN_RX_RAW_PYLD) begin : gen_adv_ta
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// Incoming MTU parameter is in CHDR_W words but eht_ipv4_chdr_adapter
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// expects it in bytes.
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localparam CPU_FIFO_SIZE = $clog2(8*(2**MTU));
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localparam CHDR_FIFO_SIZE = $clog2(8*(2**MTU));
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eth_ipv4_chdr_adapter_wrapper #(
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.PROTOVER (PROTOVER ),
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.CPU_FIFO_SIZE (CPU_FIFO_SIZE ),
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.CHDR_FIFO_SIZE (CHDR_FIFO_SIZE),
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.RT_TBL_SIZE (RT_TBL_SIZE ),
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.NODE_INST (NODE_INST ),
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.DROP_UNKNOWN_MAC(1 ),
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.PREAMBLE_BYTES (6 ),
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.CPU_PREAMBLE (1 ),
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.SYNC (1 ),
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.EN_RX_RAW_PYLD (EN_RX_RAW_PYLD)
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) eth_ipv4_chdr_adapter_wrapper_i (
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.bus_clk (clk ),
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.bus_rst (reset ),
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.device_id (device_id ),
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.my_mac (my_eth_addr ),
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.my_ip (my_ipv4_addr ),
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.my_udp_chdr_port(my_udp_chdr_port ),
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.my_pause_set (16'd0 ),
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.my_pause_clear (16'd0 ),
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.kv_stb (kv_stb ),
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.kv_busy (kv_busy ),
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.kv_mac_addr (kv_mac_addr ),
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.kv_ip_addr (kv_ip_addr ),
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.kv_udp_port (kv_udp_port ),
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.kv_dst_epid (kv_dst_epid ),
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.kv_raw_udp (kv_raw_udp ),
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.eth_clk (clk ),
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.eth_rst (reset ),
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.eth_pause_req ( ),
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.eth_tx_tdata (eth_tx_tdata ),
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.eth_tx_tuser (eth_tx_tuser ),
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.eth_tx_tkeep ( ),
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.eth_tx_tlast (eth_tx_tlast ),
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.eth_tx_tvalid (eth_tx_tvalid ),
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.eth_tx_tready (eth_tx_tready ),
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.eth_rx_tdata (eth_rx_tdata ),
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.eth_rx_tuser (eth_rx_tuser ),
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.eth_rx_tlast (eth_rx_tlast ),
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.eth_rx_tvalid (eth_rx_tvalid ),
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.eth_rx_tready (eth_rx_tready ),
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.e2v_tdata (e2v_tdata ),
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.e2v_tlast (e2v_tlast ),
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.e2v_tvalid (e2v_tvalid ),
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.e2v_tready (e2v_tready ),
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.v2e_tdata (v2e_tdata ),
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.v2e_tlast (v2e_tlast ),
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.v2e_tvalid (v2e_tvalid ),
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.v2e_tready (v2e_tready ),
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.cpu_clk (clk ),
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.cpu_rst (reset ),
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.e2c_tdata ({e2z_tdata[ 7: 0],
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e2z_tdata[15: 8],
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e2z_tdata[23:16],
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e2z_tdata[31:24],
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e2z_tdata[39:32],
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e2z_tdata[47:40],
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e2z_tdata[55:48],
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e2z_tdata[63:56]}),
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.e2c_tuser (e2z_tuser ),
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.e2c_tlast (e2z_tlast ),
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.e2c_tvalid (e2z_tvalid ),
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.e2c_tready (e2z_tready ),
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.c2e_tdata ({z2e_tdata[ 7: 0],
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z2e_tdata[15: 8],
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z2e_tdata[23:16],
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z2e_tdata[31:24],
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z2e_tdata[39:32],
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z2e_tdata[47:40],
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z2e_tdata[55:48],
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z2e_tdata[63:56]}),
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.c2e_tuser (z2e_tuser ),
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.c2e_tlast (z2e_tlast ),
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.c2e_tvalid (z2e_tvalid ),
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.c2e_tready (z2e_tready )
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);
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end else begin : gen_basic_ta
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eth_ipv4_chdr64_adapter #(
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.PROTOVER (PROTOVER),
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.MTU (MTU),
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.CPU_FIFO_SIZE (MTU),
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.RT_TBL_SIZE (RT_TBL_SIZE),
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.NODE_INST (NODE_INST),
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.DROP_UNKNOWN_MAC(1)
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) eth_ipv4_chdr64_adapter_i (
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.clk (clk ),
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.rst (reset ),
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.device_id (device_id ),
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.s_mac_tdata (eth_rx_tdata ),
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.s_mac_tuser (eth_rx_tuser ),
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.s_mac_tlast (eth_rx_tlast ),
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.s_mac_tvalid (eth_rx_tvalid ),
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.s_mac_tready (eth_rx_tready ),
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.m_mac_tdata (eth_tx_tdata ),
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.m_mac_tuser (eth_tx_tuser ),
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.m_mac_tlast (eth_tx_tlast ),
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.m_mac_tvalid (eth_tx_tvalid ),
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.m_mac_tready (eth_tx_tready ),
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.s_chdr_tdata (v2e_tdata ),
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.s_chdr_tlast (v2e_tlast ),
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.s_chdr_tvalid (v2e_tvalid ),
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.s_chdr_tready (v2e_tready ),
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.m_chdr_tdata (e2v_tdata ),
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.m_chdr_tlast (e2v_tlast ),
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.m_chdr_tvalid (e2v_tvalid ),
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.m_chdr_tready (e2v_tready ),
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.s_cpu_tdata ({z2e_tdata[7:0], z2e_tdata[15:8],
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z2e_tdata[23:16], z2e_tdata[31:24],
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z2e_tdata[39:32], z2e_tdata[47:40],
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z2e_tdata[55:48], z2e_tdata[63:56]}),
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.s_cpu_tuser (z2e_tuser ),
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.s_cpu_tlast (z2e_tlast ),
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.s_cpu_tvalid (z2e_tvalid ),
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.s_cpu_tready (z2e_tready ),
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.m_cpu_tdata ({e2z_tdata[7:0], e2z_tdata[15:8],
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e2z_tdata[23:16], e2z_tdata[31:24],
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e2z_tdata[39:32], e2z_tdata[47:40],
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e2z_tdata[55:48], e2z_tdata[63:56]}),
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.m_cpu_tuser (e2z_tuser ),
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.m_cpu_tlast (e2z_tlast ),
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.m_cpu_tvalid (e2z_tvalid ),
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.m_cpu_tready (e2z_tready ),
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.my_eth_addr (my_eth_addr ),
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.my_ipv4_addr (my_ipv4_addr ),
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.my_udp_chdr_port(my_udp_chdr_port)
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);
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end
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endmodule // x300_eth_interface
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`default_nettype wire
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