Humberto Jimenez
4082066a6f
This commit refactors the X410's CPLDs build process to make it similar to other FPGA targets within the repo. The new process relies on basic Quartus build utilities. Additionally, this commit adds support for an alternative MAX10 CPLD for the motherboard CPLD implementation. Both previous (10M04) and new variant (10M08) are supported concurrently. The images package mapping is updated to reflect these changes. Original-commit: e1ce4565dbc7336ee806adce7c087bda4fcc77ae
33 lines
811 B
Tcl
33 lines
811 B
Tcl
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Module: ps_cs_analysis
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#
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# Description:
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#
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# Analyze false path in PS SPI logic to ensure an upper delay boundary.
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#
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# get project to a working state
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project_open -force "mb_cpld.qpf"
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create_timing_netlist
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update_timing_netlist
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# Determine data path delay from MB CPLD chip select signal to MB CPLD internal
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# SPI slave
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set paths [report_path -from [get_registers {ps_spi_cs_n_decoded[0]}] -multi_corner]
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set spiSlaveCsPathDelay [lindex $paths 1]
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# clock period at 250 MHz (clock driving the decoding registers)
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set maxDelay 4
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# compare path from above with maximum delay
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if ([expr {$maxDelay < $spiSlaveCsPathDelay}]) {
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puts "MB CPLD SPI CS line longer than expected."
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exit 1
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}
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exit 0
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