Wade Fife
c322899053
This adds DRAM support to E31x devices. Due to the size of the DDR3 memory controller, it is not enabled by default. You can include the memory controller IP in the build by adding the DRAM environment variable to your build. For example: DRAM=1 make E310_SG3 Original-commit: 788fef11ef890c6dcee3be495fc381bcf2990d3b
552 lines
21 KiB
Verilog
552 lines
21 KiB
Verilog
//
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// Copyright 2022 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfnoc_image_core (for e31x)
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//
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// Description:
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//
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// The RFNoC Image Core contains the Verilog description of the RFNoC design
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// to be loaded onto the FPGA.
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//
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// File generated on: 2022-02-07T19:18:27.980096
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// Source: e310_rfnoc_image_core.yml
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// Source SHA256: 7fef622f1ae280dd7573abd823c7a6bbecf51921a74cea948e6bfb9f8f65e2cc
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//
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`default_nettype none
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module rfnoc_image_core #(
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parameter CHDR_W = 64,
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parameter MTU = 10,
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parameter [15:0] PROTOVER = {8'd1, 8'd0},
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parameter RADIO_NIPC = 1
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) (
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// Clocks
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input wire chdr_aclk,
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input wire ctrl_aclk,
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input wire core_arst,
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input wire radio_clk,
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input wire dram_clk,
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// Basic
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input wire [ 15:0] device_id,
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// IO ports /////////////////////////
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// ctrlport_radio
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output wire [ 0:0] m_ctrlport_req_wr,
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output wire [ 0:0] m_ctrlport_req_rd,
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output wire [ 19:0] m_ctrlport_req_addr,
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output wire [ 31:0] m_ctrlport_req_data,
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output wire [ 3:0] m_ctrlport_req_byte_en,
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output wire [ 0:0] m_ctrlport_req_has_time,
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output wire [ 63:0] m_ctrlport_req_time,
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input wire [ 0:0] m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [ 31:0] m_ctrlport_resp_data,
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// time_keeper
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input wire [ 63:0] radio_time,
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// x300_radio
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input wire [ 63:0] radio_rx_data,
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input wire [ 1:0] radio_rx_stb,
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output wire [ 1:0] radio_rx_running,
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output wire [ 63:0] radio_tx_data,
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input wire [ 1:0] radio_tx_stb,
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output wire [ 1:0] radio_tx_running,
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// dram
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input wire [ 0:0] axi_rst,
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output wire [ 3:0] m_axi_awid,
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output wire [ 127:0] m_axi_awaddr,
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output wire [ 31:0] m_axi_awlen,
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output wire [ 11:0] m_axi_awsize,
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output wire [ 7:0] m_axi_awburst,
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output wire [ 3:0] m_axi_awlock,
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output wire [ 15:0] m_axi_awcache,
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output wire [ 11:0] m_axi_awprot,
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output wire [ 15:0] m_axi_awqos,
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output wire [ 15:0] m_axi_awregion,
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output wire [ 3:0] m_axi_awuser,
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output wire [ 3:0] m_axi_awvalid,
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input wire [ 3:0] m_axi_awready,
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output wire [ 255:0] m_axi_wdata,
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output wire [ 31:0] m_axi_wstrb,
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output wire [ 3:0] m_axi_wlast,
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output wire [ 3:0] m_axi_wuser,
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output wire [ 3:0] m_axi_wvalid,
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input wire [ 3:0] m_axi_wready,
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input wire [ 3:0] m_axi_bid,
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input wire [ 7:0] m_axi_bresp,
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input wire [ 3:0] m_axi_buser,
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input wire [ 3:0] m_axi_bvalid,
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output wire [ 3:0] m_axi_bready,
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output wire [ 3:0] m_axi_arid,
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output wire [ 127:0] m_axi_araddr,
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output wire [ 31:0] m_axi_arlen,
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output wire [ 11:0] m_axi_arsize,
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output wire [ 7:0] m_axi_arburst,
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output wire [ 3:0] m_axi_arlock,
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output wire [ 15:0] m_axi_arcache,
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output wire [ 11:0] m_axi_arprot,
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output wire [ 15:0] m_axi_arqos,
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output wire [ 15:0] m_axi_arregion,
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output wire [ 3:0] m_axi_aruser,
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output wire [ 3:0] m_axi_arvalid,
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input wire [ 3:0] m_axi_arready,
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input wire [ 3:0] m_axi_rid,
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input wire [ 255:0] m_axi_rdata,
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input wire [ 7:0] m_axi_rresp,
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input wire [ 3:0] m_axi_rlast,
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input wire [ 3:0] m_axi_ruser,
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input wire [ 3:0] m_axi_rvalid,
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output wire [ 3:0] m_axi_rready,
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// Transport Adapters ///////////////
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// Transport 0 (dma)
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input wire [CHDR_W-1:0] s_dma_tdata,
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input wire s_dma_tlast,
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input wire s_dma_tvalid,
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output wire s_dma_tready,
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output wire [CHDR_W-1:0] m_dma_tdata,
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output wire m_dma_tlast,
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output wire m_dma_tvalid,
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input wire m_dma_tready
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);
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localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
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wire rfnoc_chdr_clk, rfnoc_chdr_rst;
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wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
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//---------------------------------------------------------------------------
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// CHDR Crossbar
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//---------------------------------------------------------------------------
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wire [CHDR_W-1:0] xb_to_ep0_tdata ;
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wire xb_to_ep0_tlast ;
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wire xb_to_ep0_tvalid;
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wire xb_to_ep0_tready;
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wire [CHDR_W-1:0] ep0_to_xb_tdata ;
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wire ep0_to_xb_tlast ;
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wire ep0_to_xb_tvalid;
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wire ep0_to_xb_tready;
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wire [CHDR_W-1:0] xb_to_ep1_tdata ;
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wire xb_to_ep1_tlast ;
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wire xb_to_ep1_tvalid;
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wire xb_to_ep1_tready;
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wire [CHDR_W-1:0] ep1_to_xb_tdata ;
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wire ep1_to_xb_tlast ;
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wire ep1_to_xb_tvalid;
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wire ep1_to_xb_tready;
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chdr_crossbar_nxn #(
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.CHDR_W (CHDR_W),
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.NPORTS (3),
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.DEFAULT_PORT (0),
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.MTU (MTU),
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.ROUTE_TBL_SIZE (6),
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.MUX_ALLOC ("ROUND-ROBIN"),
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.OPTIMIZE ("AREA"),
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.NPORTS_MGMT (1),
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.EXT_RTCFG_PORT (0),
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.PROTOVER (PROTOVER)
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) chdr_xb_i (
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.clk (rfnoc_chdr_clk),
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.reset (rfnoc_chdr_rst),
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.device_id (device_id),
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.s_axis_tdata ({ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata }),
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.s_axis_tlast ({ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast }),
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.s_axis_tvalid ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid}),
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.s_axis_tready ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready}),
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.m_axis_tdata ({xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata }),
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.m_axis_tlast ({xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast }),
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.m_axis_tvalid ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid}),
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.m_axis_tready ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready}),
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.ext_rtcfg_stb (1'h0),
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.ext_rtcfg_addr (16'h0),
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.ext_rtcfg_data (32'h0),
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.ext_rtcfg_ack ()
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);
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//---------------------------------------------------------------------------
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// Stream Endpoints
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//---------------------------------------------------------------------------
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// If requested buffer size is 0, use the minimum SRL-based FIFO size.
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// Otherwise, make sure it's at least two MTU-sized packets.
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localparam REQ_BUFF_SIZE_EP0 = 16384;
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localparam INGRESS_BUFF_SIZE_EP0 =
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REQ_BUFF_SIZE_EP0 == 0 ? 5 :
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REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
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$clog2(REQ_BUFF_SIZE_EP0);
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wire [CHDR_W-1:0] m_ep0_out0_tdata;
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wire m_ep0_out0_tlast;
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wire m_ep0_out0_tvalid;
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wire m_ep0_out0_tready;
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wire [CHDR_W-1:0] s_ep0_in0_tdata;
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wire s_ep0_in0_tlast;
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wire s_ep0_in0_tvalid;
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wire s_ep0_in0_tready;
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wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
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wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
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wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
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wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
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chdr_stream_endpoint #(
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.PROTOVER (PROTOVER),
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.CHDR_W (CHDR_W),
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.AXIS_CTRL_EN (1),
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.AXIS_DATA_EN (1),
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.NUM_DATA_I (1),
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.NUM_DATA_O (1),
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.INST_NUM (0),
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.CTRL_XBAR_PORT (1),
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.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
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.MTU (MTU),
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.REPORT_STRM_ERRS (1)
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) ep0_i (
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_chdr_rst (rfnoc_chdr_rst),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
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.device_id (device_id),
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.s_axis_chdr_tdata (xb_to_ep0_tdata),
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.s_axis_chdr_tlast (xb_to_ep0_tlast),
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.s_axis_chdr_tvalid (xb_to_ep0_tvalid),
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.s_axis_chdr_tready (xb_to_ep0_tready),
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.m_axis_chdr_tdata (ep0_to_xb_tdata),
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.m_axis_chdr_tlast (ep0_to_xb_tlast),
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.m_axis_chdr_tvalid (ep0_to_xb_tvalid),
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.m_axis_chdr_tready (ep0_to_xb_tready),
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.s_axis_data_tdata ({s_ep0_in0_tdata}),
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.s_axis_data_tlast ({s_ep0_in0_tlast}),
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.s_axis_data_tvalid ({s_ep0_in0_tvalid}),
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.s_axis_data_tready ({s_ep0_in0_tready}),
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.m_axis_data_tdata ({m_ep0_out0_tdata}),
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.m_axis_data_tlast ({m_ep0_out0_tlast}),
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.m_axis_data_tvalid ({m_ep0_out0_tvalid}),
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.m_axis_data_tready ({m_ep0_out0_tready}),
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.s_axis_ctrl_tdata (s_ep0_ctrl_tdata),
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.s_axis_ctrl_tlast (s_ep0_ctrl_tlast),
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.s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid),
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.s_axis_ctrl_tready (s_ep0_ctrl_tready),
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.m_axis_ctrl_tdata (m_ep0_ctrl_tdata),
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.m_axis_ctrl_tlast (m_ep0_ctrl_tlast),
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.m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid),
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.m_axis_ctrl_tready (m_ep0_ctrl_tready),
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.strm_seq_err_stb (),
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.strm_data_err_stb (),
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.strm_route_err_stb (),
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.signal_data_err (1'b0)
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);
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// If requested buffer size is 0, use the minimum SRL-based FIFO size.
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// Otherwise, make sure it's at least two MTU-sized packets.
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localparam REQ_BUFF_SIZE_EP1 = 16384;
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localparam INGRESS_BUFF_SIZE_EP1 =
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REQ_BUFF_SIZE_EP1 == 0 ? 5 :
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REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
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$clog2(REQ_BUFF_SIZE_EP1);
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wire [CHDR_W-1:0] m_ep1_out0_tdata;
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wire m_ep1_out0_tlast;
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wire m_ep1_out0_tvalid;
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wire m_ep1_out0_tready;
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wire [CHDR_W-1:0] s_ep1_in0_tdata;
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wire s_ep1_in0_tlast;
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wire s_ep1_in0_tvalid;
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wire s_ep1_in0_tready;
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wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
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wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
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wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
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wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
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chdr_stream_endpoint #(
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.PROTOVER (PROTOVER),
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.CHDR_W (CHDR_W),
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.AXIS_CTRL_EN (0),
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.AXIS_DATA_EN (1),
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.NUM_DATA_I (1),
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.NUM_DATA_O (1),
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.INST_NUM (1),
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.CTRL_XBAR_PORT (2),
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.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
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.MTU (MTU),
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.REPORT_STRM_ERRS (1)
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) ep1_i (
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_chdr_rst (rfnoc_chdr_rst),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
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.device_id (device_id),
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.s_axis_chdr_tdata (xb_to_ep1_tdata),
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.s_axis_chdr_tlast (xb_to_ep1_tlast),
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.s_axis_chdr_tvalid (xb_to_ep1_tvalid),
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.s_axis_chdr_tready (xb_to_ep1_tready),
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.m_axis_chdr_tdata (ep1_to_xb_tdata),
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.m_axis_chdr_tlast (ep1_to_xb_tlast),
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.m_axis_chdr_tvalid (ep1_to_xb_tvalid),
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.m_axis_chdr_tready (ep1_to_xb_tready),
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.s_axis_data_tdata ({s_ep1_in0_tdata}),
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.s_axis_data_tlast ({s_ep1_in0_tlast}),
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.s_axis_data_tvalid ({s_ep1_in0_tvalid}),
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.s_axis_data_tready ({s_ep1_in0_tready}),
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.m_axis_data_tdata ({m_ep1_out0_tdata}),
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.m_axis_data_tlast ({m_ep1_out0_tlast}),
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.m_axis_data_tvalid ({m_ep1_out0_tvalid}),
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.m_axis_data_tready ({m_ep1_out0_tready}),
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.s_axis_ctrl_tdata (s_ep1_ctrl_tdata),
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.s_axis_ctrl_tlast (s_ep1_ctrl_tlast),
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.s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid),
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.s_axis_ctrl_tready (s_ep1_ctrl_tready),
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.m_axis_ctrl_tdata (m_ep1_ctrl_tdata),
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.m_axis_ctrl_tlast (m_ep1_ctrl_tlast),
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.m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid),
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.m_axis_ctrl_tready (m_ep1_ctrl_tready),
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.strm_seq_err_stb (),
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.strm_data_err_stb (),
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.strm_route_err_stb (),
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.signal_data_err (1'b0)
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);
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//---------------------------------------------------------------------------
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// Control Crossbar
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//---------------------------------------------------------------------------
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wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
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wire m_core_ctrl_tlast, s_core_ctrl_tlast;
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wire m_core_ctrl_tvalid, s_core_ctrl_tvalid;
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wire m_core_ctrl_tready, s_core_ctrl_tready;
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wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata;
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wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast;
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wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid;
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wire m_radio0_ctrl_tready, s_radio0_ctrl_tready;
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axis_ctrl_crossbar_nxn #(
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.WIDTH (32),
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.NPORTS (3),
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.TOPOLOGY ("TORUS"),
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.INGRESS_BUFF_SIZE(5),
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.ROUTER_BUFF_SIZE (5),
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.ROUTING_ALLOC ("WORMHOLE"),
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.SWITCH_ALLOC ("PRIO")
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) ctrl_xb_i (
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.clk (rfnoc_ctrl_clk),
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.reset (rfnoc_ctrl_rst),
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.s_axis_tdata ({m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
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.s_axis_tvalid ({m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
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.s_axis_tlast ({m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
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.s_axis_tready ({m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
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.m_axis_tdata ({s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
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.m_axis_tvalid ({s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
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.m_axis_tlast ({s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
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.m_axis_tready ({s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
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.deadlock_detected()
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);
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//---------------------------------------------------------------------------
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// RFNoC Core Kernel
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//---------------------------------------------------------------------------
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wire [(512*1)-1:0] rfnoc_core_config, rfnoc_core_status;
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rfnoc_core_kernel #(
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.PROTOVER (PROTOVER),
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.DEVICE_TYPE (16'hE310),
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.DEVICE_FAMILY ("7SERIES"),
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.SAFE_START_CLKS (0),
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.NUM_BLOCKS (1),
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.NUM_STREAM_ENDPOINTS(2),
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.NUM_ENDPOINTS_CTRL (1),
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.NUM_TRANSPORTS (1),
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.NUM_EDGES (4),
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.CHDR_XBAR_PRESENT (1),
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.EDGE_TBL_FILE (EDGE_TBL_FILE)
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) core_kernel_i (
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.chdr_aclk (chdr_aclk),
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.chdr_aclk_locked (1'b1),
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.ctrl_aclk (ctrl_aclk),
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.ctrl_aclk_locked (1'b1),
|
|
.core_arst (core_arst),
|
|
.core_chdr_clk (rfnoc_chdr_clk),
|
|
.core_chdr_rst (rfnoc_chdr_rst),
|
|
.core_ctrl_clk (rfnoc_ctrl_clk),
|
|
.core_ctrl_rst (rfnoc_ctrl_rst),
|
|
.s_axis_ctrl_tdata (s_core_ctrl_tdata),
|
|
.s_axis_ctrl_tlast (s_core_ctrl_tlast),
|
|
.s_axis_ctrl_tvalid (s_core_ctrl_tvalid),
|
|
.s_axis_ctrl_tready (s_core_ctrl_tready),
|
|
.m_axis_ctrl_tdata (m_core_ctrl_tdata),
|
|
.m_axis_ctrl_tlast (m_core_ctrl_tlast),
|
|
.m_axis_ctrl_tvalid (m_core_ctrl_tvalid),
|
|
.m_axis_ctrl_tready (m_core_ctrl_tready),
|
|
.device_id (device_id),
|
|
.rfnoc_core_config (rfnoc_core_config),
|
|
.rfnoc_core_status (rfnoc_core_status)
|
|
);
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Blocks
|
|
//---------------------------------------------------------------------------
|
|
|
|
//-----------------------------------
|
|
// radio0
|
|
//-----------------------------------
|
|
|
|
wire radio0_radio_clk;
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|
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
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|
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
|
|
wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid;
|
|
wire s_radio0_in_1_tready, s_radio0_in_0_tready;
|
|
wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ;
|
|
wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ;
|
|
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
|
|
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
|
|
|
|
// ctrl_port
|
|
wire [ 0:0] radio0_m_ctrlport_req_wr;
|
|
wire [ 0:0] radio0_m_ctrlport_req_rd;
|
|
wire [ 19:0] radio0_m_ctrlport_req_addr;
|
|
wire [ 31:0] radio0_m_ctrlport_req_data;
|
|
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
|
|
wire [ 0:0] radio0_m_ctrlport_req_has_time;
|
|
wire [ 63:0] radio0_m_ctrlport_req_time;
|
|
wire [ 0:0] radio0_m_ctrlport_resp_ack;
|
|
wire [ 1:0] radio0_m_ctrlport_resp_status;
|
|
wire [ 31:0] radio0_m_ctrlport_resp_data;
|
|
// time_keeper
|
|
wire [ 63:0] radio0_radio_time;
|
|
// x300_radio
|
|
wire [ 63:0] radio0_radio_rx_data;
|
|
wire [ 1:0] radio0_radio_rx_stb;
|
|
wire [ 1:0] radio0_radio_rx_running;
|
|
wire [ 63:0] radio0_radio_tx_data;
|
|
wire [ 1:0] radio0_radio_tx_stb;
|
|
wire [ 1:0] radio0_radio_tx_running;
|
|
|
|
rfnoc_block_radio #(
|
|
.THIS_PORTID (2),
|
|
.CHDR_W (CHDR_W),
|
|
.NUM_PORTS (2),
|
|
.MTU (MTU)
|
|
) b_radio0_0 (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
|
.radio_clk (radio0_radio_clk),
|
|
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
|
|
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
|
|
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
|
|
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
|
|
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
|
|
.m_ctrlport_req_data (radio0_m_ctrlport_req_data),
|
|
.m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en),
|
|
.m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time),
|
|
.m_ctrlport_req_time (radio0_m_ctrlport_req_time),
|
|
.m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack),
|
|
.m_ctrlport_resp_status(radio0_m_ctrlport_resp_status),
|
|
.m_ctrlport_resp_data(radio0_m_ctrlport_resp_data),
|
|
.radio_time (radio0_radio_time),
|
|
.radio_rx_data (radio0_radio_rx_data),
|
|
.radio_rx_stb (radio0_radio_rx_stb),
|
|
.radio_rx_running (radio0_radio_rx_running),
|
|
.radio_tx_data (radio0_radio_tx_data),
|
|
.radio_tx_stb (radio0_radio_tx_stb),
|
|
.radio_tx_running (radio0_radio_tx_running),
|
|
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
|
|
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
|
|
.s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
|
|
.s_rfnoc_chdr_tready ({s_radio0_in_1_tready, s_radio0_in_0_tready}),
|
|
.m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }),
|
|
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
|
|
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
|
|
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
|
|
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
|
|
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
|
|
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
|
|
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
|
|
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
|
|
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
|
|
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
|
|
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
|
|
);
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Static Router
|
|
//---------------------------------------------------------------------------
|
|
|
|
assign s_radio0_in_0_tdata = m_ep0_out0_tdata;
|
|
assign s_radio0_in_0_tlast = m_ep0_out0_tlast;
|
|
assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
|
|
assign m_ep0_out0_tready = s_radio0_in_0_tready;
|
|
|
|
assign s_radio0_in_1_tdata = m_ep1_out0_tdata;
|
|
assign s_radio0_in_1_tlast = m_ep1_out0_tlast;
|
|
assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid;
|
|
assign m_ep1_out0_tready = s_radio0_in_1_tready;
|
|
|
|
assign s_ep0_in0_tdata = m_radio0_out_0_tdata;
|
|
assign s_ep0_in0_tlast = m_radio0_out_0_tlast;
|
|
assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid;
|
|
assign m_radio0_out_0_tready = s_ep0_in0_tready;
|
|
|
|
assign s_ep1_in0_tdata = m_radio0_out_1_tdata;
|
|
assign s_ep1_in0_tlast = m_radio0_out_1_tlast;
|
|
assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid;
|
|
assign m_radio0_out_1_tready = s_ep1_in0_tready;
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Unused Ports
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Clock Domains
|
|
//---------------------------------------------------------------------------
|
|
|
|
assign radio0_radio_clk = radio_clk;
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// IO Port Connection
|
|
//---------------------------------------------------------------------------
|
|
|
|
// Master/Slave Connections:
|
|
assign m_ctrlport_req_wr = radio0_m_ctrlport_req_wr;
|
|
assign m_ctrlport_req_rd = radio0_m_ctrlport_req_rd;
|
|
assign m_ctrlport_req_addr = radio0_m_ctrlport_req_addr;
|
|
assign m_ctrlport_req_data = radio0_m_ctrlport_req_data;
|
|
assign m_ctrlport_req_byte_en = radio0_m_ctrlport_req_byte_en;
|
|
assign m_ctrlport_req_has_time = radio0_m_ctrlport_req_has_time;
|
|
assign m_ctrlport_req_time = radio0_m_ctrlport_req_time;
|
|
assign radio0_m_ctrlport_resp_ack = m_ctrlport_resp_ack;
|
|
assign radio0_m_ctrlport_resp_status = m_ctrlport_resp_status;
|
|
assign radio0_m_ctrlport_resp_data = m_ctrlport_resp_data;
|
|
|
|
assign radio0_radio_rx_data = radio_rx_data;
|
|
assign radio0_radio_rx_stb = radio_rx_stb;
|
|
assign radio_rx_running = radio0_radio_rx_running;
|
|
assign radio_tx_data = radio0_radio_tx_data;
|
|
assign radio0_radio_tx_stb = radio_tx_stb;
|
|
assign radio_tx_running = radio0_radio_tx_running;
|
|
|
|
// Broadcaster/Listener Connections:
|
|
assign radio0_radio_time = radio_time;
|
|
|
|
endmodule
|
|
|
|
|
|
`default_nettype wire
|