Andrew Moch
23be04661f
Components are connected together with AxiStreamIfc. Some features
include:
(1) Add bytes to the start of a packet
(2) Remove bytes from a packet
(3) Wrappers for some older components
a. fifo - buffer but imediately pass a packet
b. packet_gate - buffer and hold till end of packet
c. width_conv - cross clock domains and change width of axi bus
The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can
be used to connect to ports with continuous assignment.
AxiStreamPacketIf must be used procedurally but allows the following
new methods:
- reached_packet_byte - notify when tdata contains a paritcular byte
- get_packet_byte/get_packet_field - extract a byte or field from axi
- put_packet_byte/put_packet_field - overwrite a byte or field onto axi
Original-commit: c3bca6c87700054c96320de119a58f6a688dbd5a
20 lines
653 B
Plaintext
20 lines
653 B
Plaintext
# This file contains all testbenches to exlcude from the filter
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# list discovered by run_testbenches.py
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# NOTE: Lines containing "#" are treated as a comment
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lib/rfnoc/noc_block_eq_tb
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lib/rfnoc/noc_block_ofdm_tb
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lib/rfnoc/noc_block_schmidl_cox_tb
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top/e31x/sim/dram_test
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top/n3xx/sim/arm_to_sfp_loopback
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top/n3xx/sim/aurora_loopback
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top/n3xx/sim/one_gig_eth_loopback
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top/n3xx/sim/ten_gig_eth_loopback
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top/x300/sim/x300_pcie_int
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top/n3xx/dboards/eiscat/radio/noc_block_ddc_eiscat_tb
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top/n3xx/dboards/eiscat/radio/noc_block_radio_core_eiscat_tb
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# These testbenches only work in ModelSim
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lib/axi4s_sv/axi4s_remove_bytes_tb
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lib/axi4s_sv/axi4s_add_bytes_tb
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