Max Köhler 2a8ec5df90 fpga: tools: remove temporary Xilinx directories for BD recreation ...

During recreation of block diagrams any RTL modules will be kept in
hidden directories within the build directory. Updates of the RTL
sources might not be taken into account. Solution is to remove Xilinx's
hidden project directories before calling vivado.


Original-commit: f17a5113e228ac1bc5312193eb8f687e127184a3

2020-06-15 13:54:35 -05:00

..

viv_design_builder.mak

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_hls_ip_builder.mak

fpga: tools: Add contents of directories for HDL source

2020-05-26 13:36:55 -05:00

viv_ip_builder.mak

fpga: tools: remove temporary Xilinx directories for BD recreation

2020-06-15 13:54:35 -05:00

viv_preamble.mak

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

viv_sim_preamble.mak

fpga: tools: Add modelsim to make sim targets

2020-03-20 10:34:59 -05:00

viv_simulator.mak

fpga: tools: Allow multiple top modules with ModelSim

2020-06-11 09:53:00 -05:00