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michael-west 8332f5b161 fpga: Fix sc16 to sc12 converter 
Re-wrote converter to remove clock cycle delay on i_tready when handling
residual output and fixed improper handling of tlast during residual
data processing.  Resolves some USB overflow issues when using sc12 data
type on B200 devices.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 1fecf446e0358aa2b6a2d1f73a0daeac516435a0
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.gitignore
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build_8_to_16
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build_12_to_16
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build_16_to_8
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build_16_to_12
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chdr_8s_to_16s.v
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chdr_8sc_to_16sc_tb.v
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chdr_8sc_to_16sc.hex
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chdr_8sc_to_16sc.v
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chdr_12sc_to_16sc_tb.v
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chdr_16sc_to_12sc_tb.v
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chdr_16sc_to_12sc.v
fpga: Fix sc16 to sc12 converter
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chdr_16sc_to_32f_tb.v
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context_packet_gen.v
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float_to_iq_tb.v
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float_to_iq.v
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from8_to_x.hex
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from12_to_x.hex
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from16_to_x.hex
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generate_bits.cpp
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iq_to_float_input.txt
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iq_to_float_output.txt
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iq_to_float_tb.v
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Makefile.srcs
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