128 lines
3.4 KiB
Systemverilog
128 lines
3.4 KiB
Systemverilog
//
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// Copyright 2020 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: PkgCtrlIfaceBfm
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//
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// Description: This package includes high-level bus functional models (BFM)
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// for the AXIS-Ctrl interface of a Stream Endpoint.
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//
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package PkgCtrlIfaceBfm;
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import rfnoc_chdr_utils_pkg::*;
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import PkgAxisCtrlBfm::*;
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class CtrlIfaceBfm extends AxisCtrlBfm;
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ctrl_port_t dst_port;
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ctrl_port_t src_port;
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ctrl_seq_num_t seq_num;
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// Class constructor to create a new BFM instance.
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//
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// m_chdr: Interface for the master connection (BFM's AXIS output)
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// s_chdr: Interface for the slave connection (BFM's AXIS input)
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// src_port: Source port to use in generated control packets
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//
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function new(
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virtual AxiStreamIf #(32).master m_chdr,
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virtual AxiStreamIf #(32).slave s_chdr,
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ctrl_port_t dst_port,
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ctrl_port_t src_port
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);
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super.new(m_chdr, s_chdr);
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this.dst_port = dst_port;
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this.src_port = src_port;
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this.seq_num = '0;
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endfunction : new
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// Send an AXIS-Ctrl read request packet and get the response.
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//
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// addr: Address for the read request
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// word: Data word that was returned in response to the read
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//
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task reg_read (
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input ctrl_address_t addr,
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output ctrl_word_t word
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);
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AxisCtrlPacket ctrl_packet;
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// Create the AXIS-Ctrl packet
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ctrl_packet = new();
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ctrl_packet.header = '{
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seq_num : seq_num++,
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num_data : 1,
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src_port : src_port,
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dst_port : dst_port,
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default : 0
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};
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ctrl_packet.op_word = '{
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status : CTRL_STS_OKAY,
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op_code : CTRL_OP_READ,
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byte_enable : '1,
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address : addr,
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default : 0
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};
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ctrl_packet.data = { 0 };
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// Send the control packet and get the response
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put_ctrl(ctrl_packet);
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get_ctrl(ctrl_packet);
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word = ctrl_packet.data[0];
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assert(ctrl_packet.header.is_ack == 1 &&
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ctrl_packet.op_word.status == CTRL_STS_OKAY) else begin
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$fatal(1, "CtrlIfaceBfm::reg_read: Did not receive CTRL_STS_OKAY status");
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end
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endtask : reg_read
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// Send an AXIS-Ctrl write request packet and get the response.
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//
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// addr: Address for the write request
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// word: Data word to write
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//
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task reg_write (
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ctrl_address_t addr,
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ctrl_word_t word
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);
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AxisCtrlPacket ctrl_packet;
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// Create the AXIS-Ctrl packet
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ctrl_packet = new();
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ctrl_packet.header = '{
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seq_num : seq_num++,
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num_data : 1,
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src_port : src_port,
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dst_port : dst_port,
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default : 0
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};
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ctrl_packet.op_word = '{
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status : CTRL_STS_OKAY,
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op_code : CTRL_OP_WRITE,
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byte_enable : '1,
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address : addr,
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default : 0
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};
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// Send the packet and get the response
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ctrl_packet.data = { word };
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put_ctrl(ctrl_packet);
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get_ctrl(ctrl_packet);
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word = ctrl_packet.data[0];
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assert(ctrl_packet.header.is_ack == 1 &&
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ctrl_packet.op_word.status == CTRL_STS_OKAY) else begin
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$fatal(1, "CtrlIfaceBfm::reg_write: Did not receive CTRL_STS_OKAY status");
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end
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endtask : reg_write
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endclass : CtrlIfaceBfm
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endpackage : PkgCtrlIfaceBfm
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