Martin Braun c98c7ab88d fpga: Remove dupes from DESIGN_SRCS ...

In the build Makefiles, this adds a function (uniq) which removes
duplicate entries from lists. We apply this to the DESIGN_SRCS passed
to the Vivado build process. This eliminates some warnings from
duplicate source files caused by redundantly referencing source files in
the Makefiles, possibly because they are listed in more than one source
file variable.


Original-commit: 1944263412d329d53b32a17e9735b79e59e319d7

2023-12-13 17:28:09 -06:00

..

diamond_design_builder.mak

fpga: tools: Lattice build flow clean-up

2022-08-03 14:28:21 -05:00

diamond_preamble.mak

fpga: Add BUILD_BASE_DIR option to makefiles

2023-02-09 07:38:49 -06:00

quartus_design_builder.mak

fpga: tools: Add Quartus build utilities

2021-12-01 10:51:07 -06:00

quartus_ip_builder.mak

fpga: tools: Add Quartus build utilities

2021-12-01 10:51:07 -06:00

quartus_preamble.mak

fpga: Add BUILD_BASE_DIR option to makefiles

2023-02-09 07:38:49 -06:00

viv_design_builder.mak

fpga: Remove dupes from DESIGN_SRCS

2023-12-13 17:28:09 -06:00

viv_hls_ip_builder.mak

fpga: tools: Fix HLS IP builder for Vivado 2021.1

2022-08-25 13:55:30 -05:00

viv_ip_builder.mak

mpm/fpga: x4xx: Major updates in preparation for future devices

2023-05-23 09:06:17 +02:00

viv_preamble.mak

fpga: Remove dupes from DESIGN_SRCS

2023-12-13 17:28:09 -06:00

viv_sim_preamble.mak

fpga: Set default part for sim in setupenv.sh

2021-08-30 08:20:10 -05:00

viv_simulator.mak

fpga: tools: Add UHD_FPGA_DIR definition to synthesis

2021-09-08 08:36:05 -05:00