+18
Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade Fife
6b67702ad7
Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade FifeThe FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
121 lines
4.1 KiB
Verilog
121 lines
4.1 KiB
Verilog
//
|
|
// Copyright 2011 Ettus Research LLC
|
|
// Copyright 2018 Ettus Research, a National Instruments Company
|
|
//
|
|
// SPDX-License-Identifier: LGPL-3.0-or-later
|
|
//
|
|
// Description
|
|
// This code implements a parameterizable true dual port memory
|
|
// (both ports can read and write). If an enable is not necessary
|
|
// it may be tied off.
|
|
//
|
|
// Note
|
|
// This module requires the ram_2port_impl.vh header file. The
|
|
// header is included multiple times with different values of
|
|
// the RAM_DIRECTIVE macro to create different implementations of the
|
|
// RAM. An implementation is chosen in ram_2port based on the
|
|
// user parameter for RAM_TYPE.
|
|
|
|
// Mode: AUTOMATIC
|
|
`define RAM_DIRECTIVE
|
|
`define RAM_MOD_NAME ram_2port_impl_auto
|
|
`include "ram_2port_impl.vh"
|
|
`undef RAM_MOD_NAME
|
|
`undef RAM_DIRECTIVE
|
|
|
|
// Mode: REG
|
|
`define RAM_DIRECTIVE (* ram_style = "registers" *)
|
|
`define RAM_MOD_NAME ram_2port_impl_reg
|
|
`include "ram_2port_impl.vh"
|
|
`undef RAM_MOD_NAME
|
|
`undef RAM_DIRECTIVE
|
|
|
|
// Mode: LUTRAM
|
|
`define RAM_DIRECTIVE (* ram_style = "distributed" *)
|
|
`define RAM_MOD_NAME ram_2port_impl_lutram
|
|
`include "ram_2port_impl.vh"
|
|
`undef RAM_MOD_NAME
|
|
`undef RAM_DIRECTIVE
|
|
|
|
// Mode: BRAM
|
|
`define RAM_DIRECTIVE (* ram_style = "block" *)
|
|
`define RAM_MOD_NAME ram_2port_impl_bram
|
|
`include "ram_2port_impl.vh"
|
|
`undef RAM_MOD_NAME
|
|
`undef RAM_DIRECTIVE
|
|
|
|
// Mode: URAM
|
|
`define RAM_DIRECTIVE (* ram_style = "ultra" *)
|
|
`define RAM_MOD_NAME ram_2port_impl_uram
|
|
`include "ram_2port_impl.vh"
|
|
`undef RAM_MOD_NAME
|
|
`undef RAM_DIRECTIVE
|
|
|
|
module ram_2port #(
|
|
parameter DWIDTH = 32, // Width of the memory block
|
|
parameter AWIDTH = 9, // log2 of the depth of the memory block
|
|
parameter RW_MODE = "READ-FIRST", // Read-write mode {READ-FIRST, WRITE-FIRST, NO-CHANGE}
|
|
parameter RAM_TYPE = "AUTOMATIC", // Type of RAM to infer {AUTOMATIC, REG, LUTRAM, BRAM, URAM}
|
|
parameter OUT_REG = 0, // Instantiate an output register? (+1 cycle of read latency)
|
|
parameter INIT_FILE = "" // Optionally initialize memory with this file
|
|
) (
|
|
input wire clka,
|
|
input wire ena,
|
|
input wire wea,
|
|
input wire [AWIDTH-1:0] addra,
|
|
input wire [DWIDTH-1:0] dia,
|
|
output wire [DWIDTH-1:0] doa,
|
|
|
|
input wire clkb,
|
|
input wire enb,
|
|
input wire web,
|
|
input wire [AWIDTH-1:0] addrb,
|
|
input wire [DWIDTH-1:0] dib,
|
|
output wire [DWIDTH-1:0] dob
|
|
);
|
|
|
|
generate
|
|
if (RAM_TYPE == "URAM")
|
|
ram_2port_impl_uram #(
|
|
.DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
|
|
.OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE)
|
|
) impl (
|
|
.clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
|
|
.clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
|
|
);
|
|
else if (RAM_TYPE == "BRAM")
|
|
ram_2port_impl_bram #(
|
|
.DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
|
|
.OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE)
|
|
) impl (
|
|
.clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
|
|
.clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
|
|
);
|
|
else if (RAM_TYPE == "LUTRAM")
|
|
ram_2port_impl_lutram #(
|
|
.DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
|
|
.OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE)
|
|
) impl (
|
|
.clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
|
|
.clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
|
|
);
|
|
else if (RAM_TYPE == "REG")
|
|
ram_2port_impl_reg #(
|
|
.DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
|
|
.OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE)
|
|
) impl (
|
|
.clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
|
|
.clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
|
|
);
|
|
else
|
|
ram_2port_impl_auto #(
|
|
.DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
|
|
.OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE)
|
|
) impl (
|
|
.clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
|
|
.clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
|
|
);
|
|
endgenerate
|
|
|
|
endmodule
|