Martin Braun
781636013c
- Adapt to coding guide - Add header that explains the module Original-commit: 09995cc9954877cb56b4f028dc273f2d5fd0be10
123 lines
3.7 KiB
Verilog
123 lines
3.7 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rx_dcoffset
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//
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// Description:
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//
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// RX Offset DC Correction Module
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// ------------------------------
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//
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// This module has two modes of operation:
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// - Automatic mode: In this case, this module acts as an IIR filter of the form
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//
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// y[k] = x[k] - alpha * y[k-1] (1)
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//
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// The module thus implements a notch filter around DC.
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//
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// - Fixed mode: In this case, a known DC offset is simply subtracted from the
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// input signal.
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//
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// IQ Operation: To fix the DC offset of an IQ signal, this module is
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// typically instantiated twice, once for the I and Q signal separately.
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//
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// Settings register:
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// This module implements a single settings bus register with configurable
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// address. The 32-bit payload of the register configures the module as
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// follows:
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// - Bit 31: When 1, use "Fixed Mode" (see above). When 0, use "Automatic Mode".
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// - Bit 30: When asserted, bits 29 through 0 are used to initialize the
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// accumulator.
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// - Bit 29:0: This sets the 30 MSBs for the accumulator. In Fixed Mode, the
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// accumulator is left unchanged and is directly subtracted from
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// the input signal.
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// In Automatic Mode, the accumulator can be primed using these
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// bits, but that is uncommon. Typically, the x[k-1] value is
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// assumed to be zero at the beginning.
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//
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// Setting the register to zero is equivalent to enabling automatic mode with
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// no initial accumulator. It may be useful to set the accumulator to zero
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// between bursts if their relative DC offset is significantly different.
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//
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// Alpha value: To avoid the usage of a multiplier in this value, the alpha
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// value is limited to powers of two, and is not runtime-configurable.
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//
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// Parameters:
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// WIDTH : Input signal width
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// ADDR : Settings bus address
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// ALPHA_SHIFT : -log2(desired_alpha), where desired_alpha is the alpha value
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// in equation (1) and must be a power of two.
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`default_nettype none
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module rx_dcoffset #(
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parameter WIDTH = 16,
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parameter ADDR = 8'd0,
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parameter ALPHA_SHIFT = 20
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) (
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input wire clk,
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input wire rst,
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// Settings bus input
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input wire set_stb,
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input wire [7:0] set_addr,
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input wire [31:0] set_data,
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// Input signal
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input wire in_stb,
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input wire [WIDTH-1:0] in,
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// Output signal
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output wire out_stb,
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output wire [WIDTH-1:0] out
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);
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localparam int_width = WIDTH + ALPHA_SHIFT;
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wire set_now = set_stb & (ADDR == set_addr);
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reg fixed; // uses fixed offset
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reg [int_width-1:0] integrator;
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reg integ_in_stb;
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wire [WIDTH-1:0] quantized;
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always @(posedge clk) begin
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if (rst) begin
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integ_in_stb <= 0;
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fixed <= 0;
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integrator <= {int_width{1'b0}};
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end else if(set_now) begin
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fixed <= set_data[31];
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if (set_data[30]) begin
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integrator <= {set_data[29:0],{(int_width-30){1'b0}}};
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end
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end else if(~fixed & in_stb) begin
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integrator <= integrator + {{(ALPHA_SHIFT){out[WIDTH-1]}},out};
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end
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integ_in_stb <= in_stb;
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end
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round_sd #(
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.WIDTH_IN(int_width),
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.WIDTH_OUT(WIDTH)
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) round_sd (
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.clk(clk),
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.reset(rst),
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.in(integrator),
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.strobe_in(integ_in_stb),
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.out(quantized),
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.strobe_out()
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);
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add2_and_clip_reg #(
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.WIDTH(WIDTH)
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) add2_and_clip_reg (
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.clk(clk),
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.rst(rst),
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.in1(in),
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.in2(-quantized),
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.strobe_in(in_stb),
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.sum(out),
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.strobe_out(out_stb)
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);
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endmodule // rx_dcoffset
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`default_nettype wire
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