1102 lines
45 KiB
Verilog
1102 lines
45 KiB
Verilog
//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfnoc_image_core (for n320)
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//
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// Description:
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//
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// The RFNoC Image Core contains the Verilog description of the RFNoC design
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// to be loaded onto the FPGA.
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//
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// Source: n320_bist_image_core.yml
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//
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`default_nettype none
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module rfnoc_image_core #(
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parameter [31:0] CHDR_W = 64,
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parameter [31:0] PORT_W = 64,
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parameter [31:0] ETH0_W = 64,
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parameter [31:0] ETH1_W = 64,
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parameter [31:0] DMA_W = 64,
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parameter MTU = 10,
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parameter [15:0] PROTOVER = {8'd1, 8'd0},
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parameter RADIO_NIPC = 1
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) (
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// Clocks
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input wire chdr_aclk,
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input wire ctrl_aclk,
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input wire core_arst,
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input wire radio_clk,
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input wire dram_clk,
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// Basic
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input wire [ 15:0] device_id,
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// IO ports /////////////////////////
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// ctrlport_radio0
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output wire [ 0:0] m_ctrlport_radio0_req_wr,
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output wire [ 0:0] m_ctrlport_radio0_req_rd,
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output wire [ 19:0] m_ctrlport_radio0_req_addr,
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output wire [ 31:0] m_ctrlport_radio0_req_data,
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output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
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output wire [ 0:0] m_ctrlport_radio0_req_has_time,
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output wire [ 63:0] m_ctrlport_radio0_req_time,
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input wire [ 0:0] m_ctrlport_radio0_resp_ack,
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input wire [ 1:0] m_ctrlport_radio0_resp_status,
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input wire [ 31:0] m_ctrlport_radio0_resp_data,
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// ctrlport_radio1
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output wire [ 0:0] m_ctrlport_radio1_req_wr,
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output wire [ 0:0] m_ctrlport_radio1_req_rd,
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output wire [ 19:0] m_ctrlport_radio1_req_addr,
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output wire [ 31:0] m_ctrlport_radio1_req_data,
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output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
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output wire [ 0:0] m_ctrlport_radio1_req_has_time,
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output wire [ 63:0] m_ctrlport_radio1_req_time,
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input wire [ 0:0] m_ctrlport_radio1_resp_ack,
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input wire [ 1:0] m_ctrlport_radio1_resp_status,
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input wire [ 31:0] m_ctrlport_radio1_resp_data,
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// time
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input wire [ 63:0] radio_time,
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// radio0
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input wire [ 255:0] radio_rx_data_radio0,
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input wire [ 7:0] radio_rx_stb_radio0,
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output wire [ 7:0] radio_rx_running_radio0,
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output wire [ 255:0] radio_tx_data_radio0,
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input wire [ 7:0] radio_tx_stb_radio0,
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output wire [ 7:0] radio_tx_running_radio0,
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// radio1
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input wire [ 255:0] radio_rx_data_radio1,
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input wire [ 7:0] radio_rx_stb_radio1,
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output wire [ 7:0] radio_rx_running_radio1,
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output wire [ 255:0] radio_tx_data_radio1,
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input wire [ 7:0] radio_tx_stb_radio1,
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output wire [ 7:0] radio_tx_running_radio1,
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// dram
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input wire [ 0:0] axi_rst,
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output wire [ 3:0] m_axi_awid,
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output wire [ 191:0] m_axi_awaddr,
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output wire [ 31:0] m_axi_awlen,
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output wire [ 11:0] m_axi_awsize,
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output wire [ 7:0] m_axi_awburst,
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output wire [ 3:0] m_axi_awlock,
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output wire [ 15:0] m_axi_awcache,
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output wire [ 11:0] m_axi_awprot,
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output wire [ 15:0] m_axi_awqos,
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output wire [ 15:0] m_axi_awregion,
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output wire [ 3:0] m_axi_awuser,
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output wire [ 3:0] m_axi_awvalid,
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input wire [ 3:0] m_axi_awready,
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output wire [2047:0] m_axi_wdata,
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output wire [ 255:0] m_axi_wstrb,
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output wire [ 3:0] m_axi_wlast,
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output wire [ 3:0] m_axi_wuser,
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output wire [ 3:0] m_axi_wvalid,
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input wire [ 3:0] m_axi_wready,
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input wire [ 3:0] m_axi_bid,
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input wire [ 7:0] m_axi_bresp,
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input wire [ 3:0] m_axi_buser,
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input wire [ 3:0] m_axi_bvalid,
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output wire [ 3:0] m_axi_bready,
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output wire [ 3:0] m_axi_arid,
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output wire [ 191:0] m_axi_araddr,
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output wire [ 31:0] m_axi_arlen,
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output wire [ 11:0] m_axi_arsize,
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output wire [ 7:0] m_axi_arburst,
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output wire [ 3:0] m_axi_arlock,
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output wire [ 15:0] m_axi_arcache,
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output wire [ 11:0] m_axi_arprot,
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output wire [ 15:0] m_axi_arqos,
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output wire [ 15:0] m_axi_arregion,
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output wire [ 3:0] m_axi_aruser,
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output wire [ 3:0] m_axi_arvalid,
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input wire [ 3:0] m_axi_arready,
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input wire [ 3:0] m_axi_rid,
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input wire [2047:0] m_axi_rdata,
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input wire [ 7:0] m_axi_rresp,
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input wire [ 3:0] m_axi_rlast,
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input wire [ 3:0] m_axi_ruser,
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input wire [ 3:0] m_axi_rvalid,
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output wire [ 3:0] m_axi_rready,
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// Transport Adapters ///////////////
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// Transport 0 (eth0)
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input wire [PORT_W-1:0] s_eth0_tdata,
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input wire s_eth0_tlast,
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input wire s_eth0_tvalid,
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output wire s_eth0_tready,
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output wire [PORT_W-1:0] m_eth0_tdata,
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output wire m_eth0_tlast,
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output wire m_eth0_tvalid,
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input wire m_eth0_tready,
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// Transport 1 (eth1)
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input wire [PORT_W-1:0] s_eth1_tdata,
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input wire s_eth1_tlast,
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input wire s_eth1_tvalid,
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output wire s_eth1_tready,
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output wire [PORT_W-1:0] m_eth1_tdata,
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output wire m_eth1_tlast,
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output wire m_eth1_tvalid,
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input wire m_eth1_tready,
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// Transport 2 (dma)
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input wire [PORT_W-1:0] s_dma_tdata,
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input wire s_dma_tlast,
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input wire s_dma_tvalid,
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output wire s_dma_tready,
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output wire [PORT_W-1:0] m_dma_tdata,
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output wire m_dma_tlast,
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output wire m_dma_tvalid,
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input wire m_dma_tready
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);
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localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
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localparam BLOCK_CHDR_W = 64;
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localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
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localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
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localparam EP0_W = 64;
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localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8);
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localparam EP1_W = 64;
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localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8);
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localparam EP4_W = 64;
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localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8);
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localparam EP5_W = 64;
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localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8);
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wire rfnoc_chdr_clk, rfnoc_chdr_rst;
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wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
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//---------------------------------------------------------------------------
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// CHDR Crossbar
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//---------------------------------------------------------------------------
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wire [PORT_W-1:0] xb_to_ep0_tdata ;
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wire xb_to_ep0_tlast ;
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wire xb_to_ep0_tvalid;
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wire xb_to_ep0_tready;
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wire [PORT_W-1:0] ep0_to_xb_tdata ;
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wire ep0_to_xb_tlast ;
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wire ep0_to_xb_tvalid;
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wire ep0_to_xb_tready;
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wire [PORT_W-1:0] xb_to_ep1_tdata ;
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wire xb_to_ep1_tlast ;
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wire xb_to_ep1_tvalid;
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wire xb_to_ep1_tready;
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wire [PORT_W-1:0] ep1_to_xb_tdata ;
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wire ep1_to_xb_tlast ;
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wire ep1_to_xb_tvalid;
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wire ep1_to_xb_tready;
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wire [PORT_W-1:0] xb_to_ep4_tdata ;
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wire xb_to_ep4_tlast ;
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wire xb_to_ep4_tvalid;
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wire xb_to_ep4_tready;
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wire [PORT_W-1:0] ep4_to_xb_tdata ;
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wire ep4_to_xb_tlast ;
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wire ep4_to_xb_tvalid;
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wire ep4_to_xb_tready;
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wire [PORT_W-1:0] xb_to_ep5_tdata ;
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wire xb_to_ep5_tlast ;
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wire xb_to_ep5_tvalid;
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wire xb_to_ep5_tready;
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wire [PORT_W-1:0] ep5_to_xb_tdata ;
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wire ep5_to_xb_tlast ;
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wire ep5_to_xb_tvalid;
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wire ep5_to_xb_tready;
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chdr_crossbar_nxn #(
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.PORT_W (PORT_W),
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.NPORTS (7),
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.CHDR_WIDTHS ({EP5_W, EP4_W, EP1_W, EP0_W, DMA_W, ETH1_W, ETH0_W}),
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.DEFAULT_PORT (0),
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.ROUTES ({ 7'b1111111,
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7'b1111111,
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7'b1111111,
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7'b1111111,
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7'b1111100,
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7'b1111010,
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7'b1111001 }),
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.BYTE_MTU (BYTE_MTU),
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.ROUTE_TBL_SIZE (6),
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.MUX_ALLOC ("ROUND-ROBIN"),
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.OPTIMIZE ("AREA"),
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.NPORTS_MGMT (3),
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.EXT_RTCFG_PORT (0),
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.PROTOVER (PROTOVER)
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) chdr_crossbar_nxn_i (
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.clk (rfnoc_chdr_clk),
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.reset (rfnoc_chdr_rst),
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.device_id (device_id),
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.s_axis_tdata ({ep5_to_xb_tdata , ep4_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth1_tdata , s_eth0_tdata }),
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.s_axis_tlast ({ep5_to_xb_tlast , ep4_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth1_tlast , s_eth0_tlast }),
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.s_axis_tvalid ({ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
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.s_axis_tready ({ep5_to_xb_tready, ep4_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}),
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.m_axis_tdata ({xb_to_ep5_tdata , xb_to_ep4_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth1_tdata , m_eth0_tdata }),
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.m_axis_tlast ({xb_to_ep5_tlast , xb_to_ep4_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth1_tlast , m_eth0_tlast }),
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.m_axis_tvalid ({xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
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.m_axis_tready ({xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}),
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.ext_rtcfg_stb (1'h0),
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.ext_rtcfg_addr (16'h0),
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.ext_rtcfg_data (32'h0),
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.ext_rtcfg_ack ()
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);
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//---------------------------------------------------------------------------
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// Stream Endpoints
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//---------------------------------------------------------------------------
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// If requested buffer size is 0, use the minimum SRL-based FIFO size.
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// Otherwise, make sure it's at least two MTU-sized packets.
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localparam REQ_BUFF_SIZE_EP0 = 32768;
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localparam INGRESS_BUFF_SIZE_EP0 =
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REQ_BUFF_SIZE_EP0 == 0 ? 5 :
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REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 :
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$clog2(REQ_BUFF_SIZE_EP0);
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wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata;
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wire m_ep0_out0_tlast;
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wire m_ep0_out0_tvalid;
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wire m_ep0_out0_tready;
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wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata;
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wire s_ep0_in0_tlast;
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wire s_ep0_in0_tvalid;
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wire s_ep0_in0_tready;
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wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
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wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
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wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
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wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
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chdr_stream_endpoint #(
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.DEVICE_FAMILY ("7SERIES"),
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.PROTOVER (PROTOVER),
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.CHDR_W (EP0_W),
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.BLOCK_CHDR_W (BLOCK_CHDR_W),
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.AXIS_CTRL_EN (1),
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.AXIS_DATA_EN (1),
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.NUM_DATA_I (1),
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.NUM_DATA_O (1),
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.INST_NUM (0),
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.CTRL_XBAR_PORT (1),
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.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
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.MTU (EP0_MTU),
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.REPORT_STRM_ERRS (1)
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) ep0_i (
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_chdr_rst (rfnoc_chdr_rst),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
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.device_id (device_id),
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.s_axis_chdr_tdata (xb_to_ep0_tdata),
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.s_axis_chdr_tlast (xb_to_ep0_tlast),
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.s_axis_chdr_tvalid (xb_to_ep0_tvalid),
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.s_axis_chdr_tready (xb_to_ep0_tready),
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.m_axis_chdr_tdata (ep0_to_xb_tdata),
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.m_axis_chdr_tlast (ep0_to_xb_tlast),
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.m_axis_chdr_tvalid (ep0_to_xb_tvalid),
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.m_axis_chdr_tready (ep0_to_xb_tready),
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.s_axis_data_tdata ({s_ep0_in0_tdata}),
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.s_axis_data_tlast ({s_ep0_in0_tlast}),
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.s_axis_data_tvalid ({s_ep0_in0_tvalid}),
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.s_axis_data_tready ({s_ep0_in0_tready}),
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.m_axis_data_tdata ({m_ep0_out0_tdata}),
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.m_axis_data_tlast ({m_ep0_out0_tlast}),
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.m_axis_data_tvalid ({m_ep0_out0_tvalid}),
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.m_axis_data_tready ({m_ep0_out0_tready}),
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.s_axis_ctrl_tdata (s_ep0_ctrl_tdata),
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.s_axis_ctrl_tlast (s_ep0_ctrl_tlast),
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.s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid),
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.s_axis_ctrl_tready (s_ep0_ctrl_tready),
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.m_axis_ctrl_tdata (m_ep0_ctrl_tdata),
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.m_axis_ctrl_tlast (m_ep0_ctrl_tlast),
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.m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid),
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.m_axis_ctrl_tready (m_ep0_ctrl_tready),
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.strm_seq_err_stb (),
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.strm_data_err_stb (),
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.strm_route_err_stb (),
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.signal_data_err (1'b0)
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);
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// If requested buffer size is 0, use the minimum SRL-based FIFO size.
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// Otherwise, make sure it's at least two MTU-sized packets.
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localparam REQ_BUFF_SIZE_EP1 = 32768;
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localparam INGRESS_BUFF_SIZE_EP1 =
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REQ_BUFF_SIZE_EP1 == 0 ? 5 :
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REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 :
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$clog2(REQ_BUFF_SIZE_EP1);
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wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata;
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wire m_ep1_out0_tlast;
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wire m_ep1_out0_tvalid;
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wire m_ep1_out0_tready;
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wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata;
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wire s_ep1_in0_tlast;
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wire s_ep1_in0_tvalid;
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wire s_ep1_in0_tready;
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wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
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wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
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wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
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wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
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chdr_stream_endpoint #(
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.DEVICE_FAMILY ("7SERIES"),
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.PROTOVER (PROTOVER),
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.CHDR_W (EP1_W),
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.BLOCK_CHDR_W (BLOCK_CHDR_W),
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.AXIS_CTRL_EN (0),
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.AXIS_DATA_EN (1),
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.NUM_DATA_I (1),
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.NUM_DATA_O (1),
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.INST_NUM (1),
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.CTRL_XBAR_PORT (2),
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.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
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.MTU (EP1_MTU),
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.REPORT_STRM_ERRS (1)
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) ep1_i (
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_chdr_rst (rfnoc_chdr_rst),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
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.device_id (device_id),
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.s_axis_chdr_tdata (xb_to_ep1_tdata),
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.s_axis_chdr_tlast (xb_to_ep1_tlast),
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.s_axis_chdr_tvalid (xb_to_ep1_tvalid),
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.s_axis_chdr_tready (xb_to_ep1_tready),
|
|
.m_axis_chdr_tdata (ep1_to_xb_tdata),
|
|
.m_axis_chdr_tlast (ep1_to_xb_tlast),
|
|
.m_axis_chdr_tvalid (ep1_to_xb_tvalid),
|
|
.m_axis_chdr_tready (ep1_to_xb_tready),
|
|
.s_axis_data_tdata ({s_ep1_in0_tdata}),
|
|
.s_axis_data_tlast ({s_ep1_in0_tlast}),
|
|
.s_axis_data_tvalid ({s_ep1_in0_tvalid}),
|
|
.s_axis_data_tready ({s_ep1_in0_tready}),
|
|
.m_axis_data_tdata ({m_ep1_out0_tdata}),
|
|
.m_axis_data_tlast ({m_ep1_out0_tlast}),
|
|
.m_axis_data_tvalid ({m_ep1_out0_tvalid}),
|
|
.m_axis_data_tready ({m_ep1_out0_tready}),
|
|
.s_axis_ctrl_tdata (s_ep1_ctrl_tdata),
|
|
.s_axis_ctrl_tlast (s_ep1_ctrl_tlast),
|
|
.s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid),
|
|
.s_axis_ctrl_tready (s_ep1_ctrl_tready),
|
|
.m_axis_ctrl_tdata (m_ep1_ctrl_tdata),
|
|
.m_axis_ctrl_tlast (m_ep1_ctrl_tlast),
|
|
.m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid),
|
|
.m_axis_ctrl_tready (m_ep1_ctrl_tready),
|
|
.strm_seq_err_stb (),
|
|
.strm_data_err_stb (),
|
|
.strm_route_err_stb (),
|
|
.signal_data_err (1'b0)
|
|
);
|
|
|
|
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
|
|
// Otherwise, make sure it's at least two MTU-sized packets.
|
|
localparam REQ_BUFF_SIZE_EP4 = 32768;
|
|
localparam INGRESS_BUFF_SIZE_EP4 =
|
|
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
|
|
REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 :
|
|
$clog2(REQ_BUFF_SIZE_EP4);
|
|
|
|
wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata;
|
|
wire m_ep4_out0_tlast;
|
|
wire m_ep4_out0_tvalid;
|
|
wire m_ep4_out0_tready;
|
|
wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata;
|
|
wire s_ep4_in0_tlast;
|
|
wire s_ep4_in0_tvalid;
|
|
wire s_ep4_in0_tready;
|
|
wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata;
|
|
wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast;
|
|
wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
|
|
wire m_ep4_ctrl_tready, s_ep4_ctrl_tready;
|
|
|
|
chdr_stream_endpoint #(
|
|
.DEVICE_FAMILY ("7SERIES"),
|
|
.PROTOVER (PROTOVER),
|
|
.CHDR_W (EP4_W),
|
|
.BLOCK_CHDR_W (BLOCK_CHDR_W),
|
|
.AXIS_CTRL_EN (0),
|
|
.AXIS_DATA_EN (1),
|
|
.NUM_DATA_I (1),
|
|
.NUM_DATA_O (1),
|
|
.INST_NUM (2),
|
|
.CTRL_XBAR_PORT (3),
|
|
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
|
|
.MTU (EP4_MTU),
|
|
.REPORT_STRM_ERRS (1)
|
|
) ep4_i (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
|
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
|
.device_id (device_id),
|
|
.s_axis_chdr_tdata (xb_to_ep4_tdata),
|
|
.s_axis_chdr_tlast (xb_to_ep4_tlast),
|
|
.s_axis_chdr_tvalid (xb_to_ep4_tvalid),
|
|
.s_axis_chdr_tready (xb_to_ep4_tready),
|
|
.m_axis_chdr_tdata (ep4_to_xb_tdata),
|
|
.m_axis_chdr_tlast (ep4_to_xb_tlast),
|
|
.m_axis_chdr_tvalid (ep4_to_xb_tvalid),
|
|
.m_axis_chdr_tready (ep4_to_xb_tready),
|
|
.s_axis_data_tdata ({s_ep4_in0_tdata}),
|
|
.s_axis_data_tlast ({s_ep4_in0_tlast}),
|
|
.s_axis_data_tvalid ({s_ep4_in0_tvalid}),
|
|
.s_axis_data_tready ({s_ep4_in0_tready}),
|
|
.m_axis_data_tdata ({m_ep4_out0_tdata}),
|
|
.m_axis_data_tlast ({m_ep4_out0_tlast}),
|
|
.m_axis_data_tvalid ({m_ep4_out0_tvalid}),
|
|
.m_axis_data_tready ({m_ep4_out0_tready}),
|
|
.s_axis_ctrl_tdata (s_ep4_ctrl_tdata),
|
|
.s_axis_ctrl_tlast (s_ep4_ctrl_tlast),
|
|
.s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid),
|
|
.s_axis_ctrl_tready (s_ep4_ctrl_tready),
|
|
.m_axis_ctrl_tdata (m_ep4_ctrl_tdata),
|
|
.m_axis_ctrl_tlast (m_ep4_ctrl_tlast),
|
|
.m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid),
|
|
.m_axis_ctrl_tready (m_ep4_ctrl_tready),
|
|
.strm_seq_err_stb (),
|
|
.strm_data_err_stb (),
|
|
.strm_route_err_stb (),
|
|
.signal_data_err (1'b0)
|
|
);
|
|
|
|
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
|
|
// Otherwise, make sure it's at least two MTU-sized packets.
|
|
localparam REQ_BUFF_SIZE_EP5 = 32768;
|
|
localparam INGRESS_BUFF_SIZE_EP5 =
|
|
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
|
|
REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 :
|
|
$clog2(REQ_BUFF_SIZE_EP5);
|
|
|
|
wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata;
|
|
wire m_ep5_out0_tlast;
|
|
wire m_ep5_out0_tvalid;
|
|
wire m_ep5_out0_tready;
|
|
wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata;
|
|
wire s_ep5_in0_tlast;
|
|
wire s_ep5_in0_tvalid;
|
|
wire s_ep5_in0_tready;
|
|
wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata;
|
|
wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast;
|
|
wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
|
|
wire m_ep5_ctrl_tready, s_ep5_ctrl_tready;
|
|
|
|
chdr_stream_endpoint #(
|
|
.DEVICE_FAMILY ("7SERIES"),
|
|
.PROTOVER (PROTOVER),
|
|
.CHDR_W (EP5_W),
|
|
.BLOCK_CHDR_W (BLOCK_CHDR_W),
|
|
.AXIS_CTRL_EN (0),
|
|
.AXIS_DATA_EN (1),
|
|
.NUM_DATA_I (1),
|
|
.NUM_DATA_O (1),
|
|
.INST_NUM (3),
|
|
.CTRL_XBAR_PORT (4),
|
|
.INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
|
|
.MTU (EP5_MTU),
|
|
.REPORT_STRM_ERRS (1)
|
|
) ep5_i (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
|
.rfnoc_chdr_rst (rfnoc_chdr_rst),
|
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
|
.device_id (device_id),
|
|
.s_axis_chdr_tdata (xb_to_ep5_tdata),
|
|
.s_axis_chdr_tlast (xb_to_ep5_tlast),
|
|
.s_axis_chdr_tvalid (xb_to_ep5_tvalid),
|
|
.s_axis_chdr_tready (xb_to_ep5_tready),
|
|
.m_axis_chdr_tdata (ep5_to_xb_tdata),
|
|
.m_axis_chdr_tlast (ep5_to_xb_tlast),
|
|
.m_axis_chdr_tvalid (ep5_to_xb_tvalid),
|
|
.m_axis_chdr_tready (ep5_to_xb_tready),
|
|
.s_axis_data_tdata ({s_ep5_in0_tdata}),
|
|
.s_axis_data_tlast ({s_ep5_in0_tlast}),
|
|
.s_axis_data_tvalid ({s_ep5_in0_tvalid}),
|
|
.s_axis_data_tready ({s_ep5_in0_tready}),
|
|
.m_axis_data_tdata ({m_ep5_out0_tdata}),
|
|
.m_axis_data_tlast ({m_ep5_out0_tlast}),
|
|
.m_axis_data_tvalid ({m_ep5_out0_tvalid}),
|
|
.m_axis_data_tready ({m_ep5_out0_tready}),
|
|
.s_axis_ctrl_tdata (s_ep5_ctrl_tdata),
|
|
.s_axis_ctrl_tlast (s_ep5_ctrl_tlast),
|
|
.s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid),
|
|
.s_axis_ctrl_tready (s_ep5_ctrl_tready),
|
|
.m_axis_ctrl_tdata (m_ep5_ctrl_tdata),
|
|
.m_axis_ctrl_tlast (m_ep5_ctrl_tlast),
|
|
.m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid),
|
|
.m_axis_ctrl_tready (m_ep5_ctrl_tready),
|
|
.strm_seq_err_stb (),
|
|
.strm_data_err_stb (),
|
|
.strm_route_err_stb (),
|
|
.signal_data_err (1'b0)
|
|
);
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Control Crossbar
|
|
//---------------------------------------------------------------------------
|
|
|
|
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
|
|
wire m_core_ctrl_tlast, s_core_ctrl_tlast;
|
|
wire m_core_ctrl_tvalid, s_core_ctrl_tvalid;
|
|
wire m_core_ctrl_tready, s_core_ctrl_tready;
|
|
wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata;
|
|
wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast;
|
|
wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid;
|
|
wire m_radio0_ctrl_tready, s_radio0_ctrl_tready;
|
|
wire [31:0] m_radio1_ctrl_tdata, s_radio1_ctrl_tdata;
|
|
wire m_radio1_ctrl_tlast, s_radio1_ctrl_tlast;
|
|
wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid;
|
|
wire m_radio1_ctrl_tready, s_radio1_ctrl_tready;
|
|
wire [31:0] m_fifo0_ctrl_tdata, s_fifo0_ctrl_tdata;
|
|
wire m_fifo0_ctrl_tlast, s_fifo0_ctrl_tlast;
|
|
wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid;
|
|
wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready;
|
|
|
|
axis_ctrl_crossbar_nxn #(
|
|
.WIDTH (32),
|
|
.NPORTS (5),
|
|
.TOPOLOGY ("TORUS"),
|
|
.INGRESS_BUFF_SIZE(5),
|
|
.ROUTER_BUFF_SIZE (5),
|
|
.ROUTING_ALLOC ("WORMHOLE"),
|
|
.SWITCH_ALLOC ("PRIO")
|
|
) ctrl_xb_i (
|
|
.clk (rfnoc_ctrl_clk),
|
|
.reset (rfnoc_ctrl_rst),
|
|
.s_axis_tdata ({m_fifo0_ctrl_tdata , m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
|
|
.s_axis_tvalid ({m_fifo0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
|
|
.s_axis_tlast ({m_fifo0_ctrl_tlast , m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
|
|
.s_axis_tready ({m_fifo0_ctrl_tready, m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
|
|
.m_axis_tdata ({s_fifo0_ctrl_tdata , s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
|
|
.m_axis_tvalid ({s_fifo0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
|
|
.m_axis_tlast ({s_fifo0_ctrl_tlast , s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
|
|
.m_axis_tready ({s_fifo0_ctrl_tready, s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
|
|
.deadlock_detected()
|
|
);
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// RFNoC Core Kernel
|
|
//---------------------------------------------------------------------------
|
|
|
|
wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status;
|
|
|
|
rfnoc_core_kernel #(
|
|
.PROTOVER (PROTOVER),
|
|
.DEVICE_TYPE (16'h1320),
|
|
.DEVICE_FAMILY ("7SERIES"),
|
|
.SAFE_START_CLKS (0),
|
|
.NUM_BLOCKS (3),
|
|
.NUM_STREAM_ENDPOINTS(4),
|
|
.NUM_ENDPOINTS_CTRL (1),
|
|
.NUM_TRANSPORTS (3),
|
|
.NUM_EDGES (8),
|
|
.CHDR_XBAR_PRESENT (1),
|
|
.EDGE_TBL_FILE (EDGE_TBL_FILE)
|
|
) core_kernel_i (
|
|
.chdr_aclk (chdr_aclk),
|
|
.chdr_aclk_locked (1'b1),
|
|
.ctrl_aclk (ctrl_aclk),
|
|
.ctrl_aclk_locked (1'b1),
|
|
.core_arst (core_arst),
|
|
.core_chdr_clk (rfnoc_chdr_clk),
|
|
.core_chdr_rst (rfnoc_chdr_rst),
|
|
.core_ctrl_clk (rfnoc_ctrl_clk),
|
|
.core_ctrl_rst (rfnoc_ctrl_rst),
|
|
.s_axis_ctrl_tdata (s_core_ctrl_tdata),
|
|
.s_axis_ctrl_tlast (s_core_ctrl_tlast),
|
|
.s_axis_ctrl_tvalid (s_core_ctrl_tvalid),
|
|
.s_axis_ctrl_tready (s_core_ctrl_tready),
|
|
.m_axis_ctrl_tdata (m_core_ctrl_tdata),
|
|
.m_axis_ctrl_tlast (m_core_ctrl_tlast),
|
|
.m_axis_ctrl_tvalid (m_core_ctrl_tvalid),
|
|
.m_axis_ctrl_tready (m_core_ctrl_tready),
|
|
.device_id (device_id),
|
|
.rfnoc_core_config (rfnoc_core_config),
|
|
.rfnoc_core_status (rfnoc_core_status)
|
|
);
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Blocks
|
|
//---------------------------------------------------------------------------
|
|
|
|
//-----------------------------------
|
|
// radio0
|
|
//-----------------------------------
|
|
|
|
wire radio0_radio_clk;
|
|
wire [BLOCK_CHDR_W-1:0] s_radio0_in_0_tdata ;
|
|
wire s_radio0_in_0_tlast ;
|
|
wire s_radio0_in_0_tvalid;
|
|
wire s_radio0_in_0_tready;
|
|
wire [BLOCK_CHDR_W-1:0] m_radio0_out_0_tdata ;
|
|
wire m_radio0_out_0_tlast ;
|
|
wire m_radio0_out_0_tvalid;
|
|
wire m_radio0_out_0_tready;
|
|
|
|
// ctrlport
|
|
wire [ 0:0] radio0_m_ctrlport_req_wr;
|
|
wire [ 0:0] radio0_m_ctrlport_req_rd;
|
|
wire [ 19:0] radio0_m_ctrlport_req_addr;
|
|
wire [ 31:0] radio0_m_ctrlport_req_data;
|
|
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
|
|
wire [ 0:0] radio0_m_ctrlport_req_has_time;
|
|
wire [ 63:0] radio0_m_ctrlport_req_time;
|
|
wire [ 0:0] radio0_m_ctrlport_resp_ack;
|
|
wire [ 1:0] radio0_m_ctrlport_resp_status;
|
|
wire [ 31:0] radio0_m_ctrlport_resp_data;
|
|
// time
|
|
wire [ 63:0] radio0_radio_time;
|
|
// radio
|
|
wire [ 255:0] radio0_radio_rx_data;
|
|
wire [ 7:0] radio0_radio_rx_stb;
|
|
wire [ 7:0] radio0_radio_rx_running;
|
|
wire [ 255:0] radio0_radio_tx_data;
|
|
wire [ 7:0] radio0_radio_tx_stb;
|
|
wire [ 7:0] radio0_radio_tx_running;
|
|
|
|
rfnoc_block_radio #(
|
|
.THIS_PORTID (2),
|
|
.CHDR_W (BLOCK_CHDR_W),
|
|
.NUM_PORTS (1),
|
|
.NIPC (1),
|
|
.ITEM_W (32),
|
|
.MTU (BLOCK_MTU)
|
|
) b_radio0_0 (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
|
.radio_clk (radio0_radio_clk),
|
|
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
|
|
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
|
|
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
|
|
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
|
|
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
|
|
.m_ctrlport_req_data (radio0_m_ctrlport_req_data),
|
|
.m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en),
|
|
.m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time),
|
|
.m_ctrlport_req_time (radio0_m_ctrlport_req_time),
|
|
.m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack),
|
|
.m_ctrlport_resp_status(radio0_m_ctrlport_resp_status),
|
|
.m_ctrlport_resp_data(radio0_m_ctrlport_resp_data),
|
|
.radio_time (radio0_radio_time),
|
|
.radio_rx_data (radio0_radio_rx_data),
|
|
.radio_rx_stb (radio0_radio_rx_stb),
|
|
.radio_rx_running (radio0_radio_rx_running),
|
|
.radio_tx_data (radio0_radio_tx_data),
|
|
.radio_tx_stb (radio0_radio_tx_stb),
|
|
.radio_tx_running (radio0_radio_tx_running),
|
|
.s_rfnoc_chdr_tdata ({s_radio0_in_0_tdata }),
|
|
.s_rfnoc_chdr_tlast ({s_radio0_in_0_tlast }),
|
|
.s_rfnoc_chdr_tvalid ({s_radio0_in_0_tvalid}),
|
|
.s_rfnoc_chdr_tready ({s_radio0_in_0_tready}),
|
|
.m_rfnoc_chdr_tdata ({m_radio0_out_0_tdata }),
|
|
.m_rfnoc_chdr_tlast ({m_radio0_out_0_tlast }),
|
|
.m_rfnoc_chdr_tvalid ({m_radio0_out_0_tvalid}),
|
|
.m_rfnoc_chdr_tready ({m_radio0_out_0_tready}),
|
|
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
|
|
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
|
|
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
|
|
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
|
|
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
|
|
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
|
|
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
|
|
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
|
|
);
|
|
|
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//-----------------------------------
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|
// radio1
|
|
//-----------------------------------
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|
|
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wire radio1_radio_clk;
|
|
wire [BLOCK_CHDR_W-1:0] s_radio1_in_0_tdata ;
|
|
wire s_radio1_in_0_tlast ;
|
|
wire s_radio1_in_0_tvalid;
|
|
wire s_radio1_in_0_tready;
|
|
wire [BLOCK_CHDR_W-1:0] m_radio1_out_0_tdata ;
|
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wire m_radio1_out_0_tlast ;
|
|
wire m_radio1_out_0_tvalid;
|
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wire m_radio1_out_0_tready;
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|
|
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// ctrlport
|
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wire [ 0:0] radio1_m_ctrlport_req_wr;
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wire [ 0:0] radio1_m_ctrlport_req_rd;
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wire [ 19:0] radio1_m_ctrlport_req_addr;
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wire [ 31:0] radio1_m_ctrlport_req_data;
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wire [ 3:0] radio1_m_ctrlport_req_byte_en;
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wire [ 0:0] radio1_m_ctrlport_req_has_time;
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wire [ 63:0] radio1_m_ctrlport_req_time;
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wire [ 0:0] radio1_m_ctrlport_resp_ack;
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wire [ 1:0] radio1_m_ctrlport_resp_status;
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wire [ 31:0] radio1_m_ctrlport_resp_data;
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// time
|
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wire [ 63:0] radio1_radio_time;
|
|
// radio
|
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wire [ 255:0] radio1_radio_rx_data;
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wire [ 7:0] radio1_radio_rx_stb;
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wire [ 7:0] radio1_radio_rx_running;
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wire [ 255:0] radio1_radio_tx_data;
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wire [ 7:0] radio1_radio_tx_stb;
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wire [ 7:0] radio1_radio_tx_running;
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|
|
|
rfnoc_block_radio #(
|
|
.THIS_PORTID (3),
|
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.CHDR_W (BLOCK_CHDR_W),
|
|
.NUM_PORTS (1),
|
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.NIPC (1),
|
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.ITEM_W (32),
|
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.MTU (BLOCK_MTU)
|
|
) b_radio1_1 (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
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.radio_clk (radio1_radio_clk),
|
|
.rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]),
|
|
.rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]),
|
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.m_ctrlport_req_wr (radio1_m_ctrlport_req_wr),
|
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.m_ctrlport_req_rd (radio1_m_ctrlport_req_rd),
|
|
.m_ctrlport_req_addr (radio1_m_ctrlport_req_addr),
|
|
.m_ctrlport_req_data (radio1_m_ctrlport_req_data),
|
|
.m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en),
|
|
.m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time),
|
|
.m_ctrlport_req_time (radio1_m_ctrlport_req_time),
|
|
.m_ctrlport_resp_ack (radio1_m_ctrlport_resp_ack),
|
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.m_ctrlport_resp_status(radio1_m_ctrlport_resp_status),
|
|
.m_ctrlport_resp_data(radio1_m_ctrlport_resp_data),
|
|
.radio_time (radio1_radio_time),
|
|
.radio_rx_data (radio1_radio_rx_data),
|
|
.radio_rx_stb (radio1_radio_rx_stb),
|
|
.radio_rx_running (radio1_radio_rx_running),
|
|
.radio_tx_data (radio1_radio_tx_data),
|
|
.radio_tx_stb (radio1_radio_tx_stb),
|
|
.radio_tx_running (radio1_radio_tx_running),
|
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.s_rfnoc_chdr_tdata ({s_radio1_in_0_tdata }),
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.s_rfnoc_chdr_tlast ({s_radio1_in_0_tlast }),
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.s_rfnoc_chdr_tvalid ({s_radio1_in_0_tvalid}),
|
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.s_rfnoc_chdr_tready ({s_radio1_in_0_tready}),
|
|
.m_rfnoc_chdr_tdata ({m_radio1_out_0_tdata }),
|
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.m_rfnoc_chdr_tlast ({m_radio1_out_0_tlast }),
|
|
.m_rfnoc_chdr_tvalid ({m_radio1_out_0_tvalid}),
|
|
.m_rfnoc_chdr_tready ({m_radio1_out_0_tready}),
|
|
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata),
|
|
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast),
|
|
.s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid),
|
|
.s_rfnoc_ctrl_tready (s_radio1_ctrl_tready),
|
|
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata),
|
|
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast),
|
|
.m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid),
|
|
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
|
|
);
|
|
|
|
//-----------------------------------
|
|
// fifo0
|
|
//-----------------------------------
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|
|
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wire fifo0_mem_clk;
|
|
wire [BLOCK_CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ;
|
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wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ;
|
|
wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid;
|
|
wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready;
|
|
wire [BLOCK_CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ;
|
|
wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ;
|
|
wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid;
|
|
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
|
|
|
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// axi_ram
|
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wire [ 0:0] fifo0_axi_rst;
|
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wire [ 3:0] fifo0_m_axi_awid;
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wire [ 191:0] fifo0_m_axi_awaddr;
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wire [ 31:0] fifo0_m_axi_awlen;
|
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wire [ 11:0] fifo0_m_axi_awsize;
|
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wire [ 7:0] fifo0_m_axi_awburst;
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wire [ 3:0] fifo0_m_axi_awlock;
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wire [ 15:0] fifo0_m_axi_awcache;
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wire [ 11:0] fifo0_m_axi_awprot;
|
|
wire [ 15:0] fifo0_m_axi_awqos;
|
|
wire [ 15:0] fifo0_m_axi_awregion;
|
|
wire [ 3:0] fifo0_m_axi_awuser;
|
|
wire [ 3:0] fifo0_m_axi_awvalid;
|
|
wire [ 3:0] fifo0_m_axi_awready;
|
|
wire [2047:0] fifo0_m_axi_wdata;
|
|
wire [ 255:0] fifo0_m_axi_wstrb;
|
|
wire [ 3:0] fifo0_m_axi_wlast;
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wire [ 3:0] fifo0_m_axi_wuser;
|
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wire [ 3:0] fifo0_m_axi_wvalid;
|
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wire [ 3:0] fifo0_m_axi_wready;
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wire [ 3:0] fifo0_m_axi_bid;
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wire [ 7:0] fifo0_m_axi_bresp;
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wire [ 3:0] fifo0_m_axi_buser;
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wire [ 3:0] fifo0_m_axi_bvalid;
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|
wire [ 3:0] fifo0_m_axi_bready;
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|
wire [ 3:0] fifo0_m_axi_arid;
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|
wire [ 191:0] fifo0_m_axi_araddr;
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|
wire [ 31:0] fifo0_m_axi_arlen;
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|
wire [ 11:0] fifo0_m_axi_arsize;
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|
wire [ 7:0] fifo0_m_axi_arburst;
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|
wire [ 3:0] fifo0_m_axi_arlock;
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|
wire [ 15:0] fifo0_m_axi_arcache;
|
|
wire [ 11:0] fifo0_m_axi_arprot;
|
|
wire [ 15:0] fifo0_m_axi_arqos;
|
|
wire [ 15:0] fifo0_m_axi_arregion;
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|
wire [ 3:0] fifo0_m_axi_aruser;
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wire [ 3:0] fifo0_m_axi_arvalid;
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wire [ 3:0] fifo0_m_axi_arready;
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|
wire [ 3:0] fifo0_m_axi_rid;
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|
wire [2047:0] fifo0_m_axi_rdata;
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wire [ 7:0] fifo0_m_axi_rresp;
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wire [ 3:0] fifo0_m_axi_rlast;
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wire [ 3:0] fifo0_m_axi_ruser;
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wire [ 3:0] fifo0_m_axi_rvalid;
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|
wire [ 3:0] fifo0_m_axi_rready;
|
|
|
|
rfnoc_block_axi_ram_fifo #(
|
|
.THIS_PORTID (4),
|
|
.CHDR_W (BLOCK_CHDR_W),
|
|
.NUM_PORTS (4),
|
|
.MEM_DATA_W (64),
|
|
.MEM_ADDR_W (31),
|
|
.FIFO_ADDR_BASE ({31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}),
|
|
.FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}),
|
|
.MEM_CLK_RATE (303819444),
|
|
.IN_FIFO_SIZE (),
|
|
.OUT_FIFO_SIZE (),
|
|
.MTU (BLOCK_MTU)
|
|
) b_fifo0_2 (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
|
.mem_clk (fifo0_mem_clk),
|
|
.rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]),
|
|
.rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]),
|
|
.axi_rst (fifo0_axi_rst),
|
|
.m_axi_awid (fifo0_m_axi_awid),
|
|
.m_axi_awaddr (fifo0_m_axi_awaddr),
|
|
.m_axi_awlen (fifo0_m_axi_awlen),
|
|
.m_axi_awsize (fifo0_m_axi_awsize),
|
|
.m_axi_awburst (fifo0_m_axi_awburst),
|
|
.m_axi_awlock (fifo0_m_axi_awlock),
|
|
.m_axi_awcache (fifo0_m_axi_awcache),
|
|
.m_axi_awprot (fifo0_m_axi_awprot),
|
|
.m_axi_awqos (fifo0_m_axi_awqos),
|
|
.m_axi_awregion (fifo0_m_axi_awregion),
|
|
.m_axi_awuser (fifo0_m_axi_awuser),
|
|
.m_axi_awvalid (fifo0_m_axi_awvalid),
|
|
.m_axi_awready (fifo0_m_axi_awready),
|
|
.m_axi_wdata (fifo0_m_axi_wdata),
|
|
.m_axi_wstrb (fifo0_m_axi_wstrb),
|
|
.m_axi_wlast (fifo0_m_axi_wlast),
|
|
.m_axi_wuser (fifo0_m_axi_wuser),
|
|
.m_axi_wvalid (fifo0_m_axi_wvalid),
|
|
.m_axi_wready (fifo0_m_axi_wready),
|
|
.m_axi_bid (fifo0_m_axi_bid),
|
|
.m_axi_bresp (fifo0_m_axi_bresp),
|
|
.m_axi_buser (fifo0_m_axi_buser),
|
|
.m_axi_bvalid (fifo0_m_axi_bvalid),
|
|
.m_axi_bready (fifo0_m_axi_bready),
|
|
.m_axi_arid (fifo0_m_axi_arid),
|
|
.m_axi_araddr (fifo0_m_axi_araddr),
|
|
.m_axi_arlen (fifo0_m_axi_arlen),
|
|
.m_axi_arsize (fifo0_m_axi_arsize),
|
|
.m_axi_arburst (fifo0_m_axi_arburst),
|
|
.m_axi_arlock (fifo0_m_axi_arlock),
|
|
.m_axi_arcache (fifo0_m_axi_arcache),
|
|
.m_axi_arprot (fifo0_m_axi_arprot),
|
|
.m_axi_arqos (fifo0_m_axi_arqos),
|
|
.m_axi_arregion (fifo0_m_axi_arregion),
|
|
.m_axi_aruser (fifo0_m_axi_aruser),
|
|
.m_axi_arvalid (fifo0_m_axi_arvalid),
|
|
.m_axi_arready (fifo0_m_axi_arready),
|
|
.m_axi_rid (fifo0_m_axi_rid),
|
|
.m_axi_rdata (fifo0_m_axi_rdata),
|
|
.m_axi_rresp (fifo0_m_axi_rresp),
|
|
.m_axi_rlast (fifo0_m_axi_rlast),
|
|
.m_axi_ruser (fifo0_m_axi_ruser),
|
|
.m_axi_rvalid (fifo0_m_axi_rvalid),
|
|
.m_axi_rready (fifo0_m_axi_rready),
|
|
.s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }),
|
|
.s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }),
|
|
.s_rfnoc_chdr_tvalid ({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}),
|
|
.s_rfnoc_chdr_tready ({s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready}),
|
|
.m_rfnoc_chdr_tdata ({m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }),
|
|
.m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }),
|
|
.m_rfnoc_chdr_tvalid ({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}),
|
|
.m_rfnoc_chdr_tready ({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}),
|
|
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata),
|
|
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast),
|
|
.s_rfnoc_ctrl_tvalid (s_fifo0_ctrl_tvalid),
|
|
.s_rfnoc_ctrl_tready (s_fifo0_ctrl_tready),
|
|
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata),
|
|
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast),
|
|
.m_rfnoc_ctrl_tvalid (m_fifo0_ctrl_tvalid),
|
|
.m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready)
|
|
);
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Static Router
|
|
//---------------------------------------------------------------------------
|
|
|
|
assign s_radio0_in_0_tdata = m_ep0_out0_tdata;
|
|
assign s_radio0_in_0_tlast = m_ep0_out0_tlast;
|
|
assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
|
|
assign m_ep0_out0_tready = s_radio0_in_0_tready;
|
|
|
|
assign s_ep0_in0_tdata = m_radio0_out_0_tdata;
|
|
assign s_ep0_in0_tlast = m_radio0_out_0_tlast;
|
|
assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid;
|
|
assign m_radio0_out_0_tready = s_ep0_in0_tready;
|
|
|
|
assign s_radio1_in_0_tdata = m_ep1_out0_tdata;
|
|
assign s_radio1_in_0_tlast = m_ep1_out0_tlast;
|
|
assign s_radio1_in_0_tvalid = m_ep1_out0_tvalid;
|
|
assign m_ep1_out0_tready = s_radio1_in_0_tready;
|
|
|
|
assign s_ep1_in0_tdata = m_radio1_out_0_tdata;
|
|
assign s_ep1_in0_tlast = m_radio1_out_0_tlast;
|
|
assign s_ep1_in0_tvalid = m_radio1_out_0_tvalid;
|
|
assign m_radio1_out_0_tready = s_ep1_in0_tready;
|
|
|
|
assign s_fifo0_in_0_tdata = m_ep4_out0_tdata;
|
|
assign s_fifo0_in_0_tlast = m_ep4_out0_tlast;
|
|
assign s_fifo0_in_0_tvalid = m_ep4_out0_tvalid;
|
|
assign m_ep4_out0_tready = s_fifo0_in_0_tready;
|
|
|
|
assign s_ep4_in0_tdata = m_fifo0_out_0_tdata;
|
|
assign s_ep4_in0_tlast = m_fifo0_out_0_tlast;
|
|
assign s_ep4_in0_tvalid = m_fifo0_out_0_tvalid;
|
|
assign m_fifo0_out_0_tready = s_ep4_in0_tready;
|
|
|
|
assign s_fifo0_in_1_tdata = m_ep5_out0_tdata;
|
|
assign s_fifo0_in_1_tlast = m_ep5_out0_tlast;
|
|
assign s_fifo0_in_1_tvalid = m_ep5_out0_tvalid;
|
|
assign m_ep5_out0_tready = s_fifo0_in_1_tready;
|
|
|
|
assign s_ep5_in0_tdata = m_fifo0_out_1_tdata;
|
|
assign s_ep5_in0_tlast = m_fifo0_out_1_tlast;
|
|
assign s_ep5_in0_tvalid = m_fifo0_out_1_tvalid;
|
|
assign m_fifo0_out_1_tready = s_ep5_in0_tready;
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Unused Ports
|
|
//---------------------------------------------------------------------------
|
|
|
|
assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}};
|
|
assign s_fifo0_in_2_tlast = 1'b0;
|
|
assign s_fifo0_in_2_tvalid = 1'b0;
|
|
assign s_fifo0_in_3_tdata = {CHDR_W{1'b0}};
|
|
assign s_fifo0_in_3_tlast = 1'b0;
|
|
assign s_fifo0_in_3_tvalid = 1'b0;
|
|
assign m_fifo0_out_2_tready = 1'b1;
|
|
assign m_fifo0_out_3_tready = 1'b1;
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Clock Domains
|
|
//---------------------------------------------------------------------------
|
|
|
|
assign radio0_radio_clk = radio_clk;
|
|
assign radio1_radio_clk = radio_clk;
|
|
assign fifo0_mem_clk = dram_clk;
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// IO Port Connection
|
|
//---------------------------------------------------------------------------
|
|
|
|
// Master/Slave Connections:
|
|
assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr;
|
|
assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd;
|
|
assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr;
|
|
assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data;
|
|
assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en;
|
|
assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time;
|
|
assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time;
|
|
assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack;
|
|
assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status;
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assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data;
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assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr;
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assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd;
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assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr;
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assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data;
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assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en;
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assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time;
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assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time;
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assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack;
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assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
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assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
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assign fifo0_axi_rst = axi_rst;
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assign m_axi_awid = fifo0_m_axi_awid;
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assign m_axi_awaddr = fifo0_m_axi_awaddr;
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assign m_axi_awlen = fifo0_m_axi_awlen;
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assign m_axi_awsize = fifo0_m_axi_awsize;
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assign m_axi_awburst = fifo0_m_axi_awburst;
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assign m_axi_awlock = fifo0_m_axi_awlock;
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assign m_axi_awcache = fifo0_m_axi_awcache;
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assign m_axi_awprot = fifo0_m_axi_awprot;
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assign m_axi_awqos = fifo0_m_axi_awqos;
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assign m_axi_awregion = fifo0_m_axi_awregion;
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assign m_axi_awuser = fifo0_m_axi_awuser;
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assign m_axi_awvalid = fifo0_m_axi_awvalid;
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assign fifo0_m_axi_awready = m_axi_awready;
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assign m_axi_wdata = fifo0_m_axi_wdata;
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assign m_axi_wstrb = fifo0_m_axi_wstrb;
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assign m_axi_wlast = fifo0_m_axi_wlast;
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assign m_axi_wuser = fifo0_m_axi_wuser;
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assign m_axi_wvalid = fifo0_m_axi_wvalid;
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assign fifo0_m_axi_wready = m_axi_wready;
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assign fifo0_m_axi_bid = m_axi_bid;
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assign fifo0_m_axi_bresp = m_axi_bresp;
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assign fifo0_m_axi_buser = m_axi_buser;
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assign fifo0_m_axi_bvalid = m_axi_bvalid;
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assign m_axi_bready = fifo0_m_axi_bready;
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assign m_axi_arid = fifo0_m_axi_arid;
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assign m_axi_araddr = fifo0_m_axi_araddr;
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assign m_axi_arlen = fifo0_m_axi_arlen;
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assign m_axi_arsize = fifo0_m_axi_arsize;
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assign m_axi_arburst = fifo0_m_axi_arburst;
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assign m_axi_arlock = fifo0_m_axi_arlock;
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assign m_axi_arcache = fifo0_m_axi_arcache;
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assign m_axi_arprot = fifo0_m_axi_arprot;
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assign m_axi_arqos = fifo0_m_axi_arqos;
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assign m_axi_arregion = fifo0_m_axi_arregion;
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assign m_axi_aruser = fifo0_m_axi_aruser;
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assign m_axi_arvalid = fifo0_m_axi_arvalid;
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assign fifo0_m_axi_arready = m_axi_arready;
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assign fifo0_m_axi_rid = m_axi_rid;
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assign fifo0_m_axi_rdata = m_axi_rdata;
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assign fifo0_m_axi_rresp = m_axi_rresp;
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assign fifo0_m_axi_rlast = m_axi_rlast;
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assign fifo0_m_axi_ruser = m_axi_ruser;
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assign fifo0_m_axi_rvalid = m_axi_rvalid;
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assign m_axi_rready = fifo0_m_axi_rready;
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assign radio0_radio_rx_data = radio_rx_data_radio0;
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assign radio0_radio_rx_stb = radio_rx_stb_radio0;
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assign radio_rx_running_radio0 = radio0_radio_rx_running;
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assign radio_tx_data_radio0 = radio0_radio_tx_data;
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assign radio0_radio_tx_stb = radio_tx_stb_radio0;
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assign radio_tx_running_radio0 = radio0_radio_tx_running;
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assign radio1_radio_rx_data = radio_rx_data_radio1;
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assign radio1_radio_rx_stb = radio_rx_stb_radio1;
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assign radio_rx_running_radio1 = radio1_radio_rx_running;
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assign radio_tx_data_radio1 = radio1_radio_tx_data;
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assign radio1_radio_tx_stb = radio_tx_stb_radio1;
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assign radio_tx_running_radio1 = radio1_radio_tx_running;
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// Broadcaster/Listener Connections:
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assign radio0_radio_time = radio_time;
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assign radio1_radio_time = radio_time;
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endmodule
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`default_nettype wire
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