Ryan Marlow
0817f084a3
This module wraps i2c_master_top to provide a CtrlPort Interface. Original-commit: adceebe070d5b15be434aa07961958dafedf5095
37 lines
1.3 KiB
Systemverilog
37 lines
1.3 KiB
Systemverilog
//
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Header File: i2c_master.vh
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//
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// Description: Additional parameter definitions used by modules that instance
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// the i2c_master_top wb<->I2C core.
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//===============================================================================
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// WB Registers defined in i2c_master_top
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//===============================================================================
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localparam WB_PRER_LO = 3'b000;
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localparam WB_PRER_HI = 3'b001;
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localparam WB_CTR = 3'b010;
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localparam WB_RXR = 3'b011;
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localparam WB_TXR = 3'b011;
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localparam WB_CR = 3'b100;
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localparam WB_SR = 3'b100;
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//===============================================================================
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// Valid CR (Command Register) commands
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//===============================================================================
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localparam CR_START_AND_WRITE = 'h90;
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localparam CR_WRITE = 'h10;
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localparam CR_WRITE_AND_STOP = 'h50;
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localparam CR_READ_AND_ACK = 'h20;
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localparam CR_READ_AND_NACK = 'h28;
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//===============================================================================
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// WB Core Enable command
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//===============================================================================
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localparam WB_CORE_EN = 'h80;
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