adf6f576c6
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
37 lines
1.5 KiB
Systemverilog
37 lines
1.5 KiB
Systemverilog
//
|
|
// Copyright 2023 Ettus Research, A National Instruments Company
|
|
//
|
|
// SPDX-License-Identifier: LGPL-3.0-or-later
|
|
//
|
|
// Module: radio_dio_regmap_utils.vh
|
|
// Description:
|
|
// The constants in this file are autogenerated by XmlParse.
|
|
|
|
//===============================================================================
|
|
// A numerically ordered list of registers and their HDL source files
|
|
//===============================================================================
|
|
|
|
// RADIO_GPIO_ATR_REGS : 0x0 (x4xx_core_common.v)
|
|
// DIO_SOURCE_CONTROL : 0x1000 (x4xx_core_common.v)
|
|
// DIGITAL_IFC_REGS : 0x2000 (x4xx_core_common.v)
|
|
|
|
//===============================================================================
|
|
// RegTypes
|
|
//===============================================================================
|
|
|
|
//===============================================================================
|
|
// Register Group DIO_SOURCES
|
|
//===============================================================================
|
|
|
|
// RADIO_GPIO_ATR_REGS Window (from x4xx_core_common.v)
|
|
localparam RADIO_GPIO_ATR_REGS = 'h0; // Window Offset
|
|
localparam RADIO_GPIO_ATR_REGS_SIZE = 'h1000; // size in bytes
|
|
|
|
// DIO_SOURCE_CONTROL Window (from x4xx_core_common.v)
|
|
localparam DIO_SOURCE_CONTROL = 'h1000; // Window Offset
|
|
localparam DIO_SOURCE_CONTROL_SIZE = 'h1000; // size in bytes
|
|
|
|
// DIGITAL_IFC_REGS Window (from x4xx_core_common.v)
|
|
localparam DIGITAL_IFC_REGS = 'h2000; // Window Offset
|
|
localparam DIGITAL_IFC_REGS_SIZE = 'h1000; // size in bytes
|