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Max Köhler c48f8bd5f1 fpga: rfnoc: lib: add AXI FIR filter for >1 SPC 
Original-commit: 90ad1fecb62b804f543def6e4c680706d76442b5
2025-02-13 08:28:46 -06:00
..
sim
fpga: rfnoc: lib: add AXI FIR filter for >1 SPC
2025-02-13 08:28:46 -06:00
acc.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
add2_and_clip_reg.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
add2_and_clip.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
add2_and_round_reg.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
add2_and_round.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
add2_reg.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
add2.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
add_then_mac.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fir_multisample_filter.sv
fpga: rfnoc: lib: add AXI FIR filter for >1 SPC
2025-02-13 08:28:46 -06:00
cic_dec_shifter.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cic_decim.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cic_int_shifter.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cic_interp.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cic_strober.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
clip_reg.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
clip.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cordic_stage.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cordic_z24.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ddc_chain.v
fpga/usrp3: Fix DC truncation bias by adding rounding to DDC chain.
2024-06-11 10:20:08 +02:00
duc_chain.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
hb47_int_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
hb47_int.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
hb_dec.v
fpga/usrp3: Fix DC truncation bias by adding rounding to DDC chain.
2024-06-11 10:20:08 +02:00
hb_interp.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.srcs
fpga: rfnoc: lib: add AXI FIR filter for >1 SPC
2025-02-13 08:28:46 -06:00
mult_add_clip.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
round_reg.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
round_sd.v
fpga: lib: Update round_sd to eliminate X from simulation
2021-04-09 17:26:59 -05:00
round.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
rx_dcoffset.v
fpga: dsp: Fix formatting of rx_dcoffset and add docs
2021-03-09 08:33:32 -06:00
rx_frontend_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
rx_frontend.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
sign_extend.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
small_hb_dec.v
fpga/usrp3: Fix DC truncation bias by adding rounding to DDC chain.
2024-06-11 10:20:08 +02:00
small_hb_int.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
srl.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
tx_frontend.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
variable_delay_line.v
fpga: rfnoc: Add Vector IIR RFNoC block
2020-05-19 14:22:55 -05:00