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845dfd4f8740dab9ce14478e8de1b72e73dd4eba
b210-k7-fpga/top/n3xx/dboards/rh/cpld/rhodium_top.qsf
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Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade Fife
 6b67702ad7 Merge FPGA repository back into UHD repository 
The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>


Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
2020-01-28 09:35:36 -08:00

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition
# Date created = 08:22:34 September 13, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# rhodium_top_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M04SAU169I7G
set_global_assignment -name TOP_LEVEL_ENTITY rhodium_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:22:34 SEPTEMBER 13, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_D11 -to CPLD_PS_SPI_LE_25
set_location_assignment PIN_F13 -to CPLD_PS_SPI_CLK_25
set_location_assignment PIN_E10 -to CPLD_PS_ADDR0_25
set_location_assignment PIN_A12 -to CPLD_PS_ADDR1_25
set_location_assignment PIN_F12 -to CPLD_PS_SPI_SDI_25
set_location_assignment PIN_F10 -to CPLD_PS_SPI_SDO_25
set_location_assignment PIN_B1 -to ADC_A_Over_Range_18
set_location_assignment PIN_D1 -to ADC_B_Over_Range_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_A_Over_Range_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_B_Over_Range_18
set_instance_assignment -name IO_STANDARD LVDS -to LO_SYNC
set_location_assignment PIN_G9 -to LO_SYNC
set_location_assignment PIN_G10 -to "LO_SYNC(n)"
set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_CS_L_18
set_location_assignment PIN_C2 -to ADC_SPI_CS_L_18
set_location_assignment PIN_C1 -to ADC_SPI_SCLK_18
set_location_assignment PIN_E3 -to ADC_SPI_SDIO_18
set_location_assignment PIN_M5 -to CLKDIST_SPI_CS_L
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_CS_L
set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_SCLK_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_SDIO_18
set_location_assignment PIN_L5 -to CLKDIST_SPI_SCLK
set_location_assignment PIN_N5 -to CLKDIST_SPI_SDIO
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_SDIO
set_location_assignment PIN_K6 -to CLKDIST_Status_LD1
set_location_assignment PIN_J6 -to CLKDIST_Status_LD2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_Status_LD1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_Status_LD2
set_location_assignment PIN_M1 -to CPLD_ATR_TX_18
set_location_assignment PIN_L1 -to CPLD_ATR_RX_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_ATR_RX_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_ATR_TX_18
set_location_assignment PIN_H6 -to CPLD_PL_SPI_ADDR0_18
set_location_assignment PIN_K2 -to CPLD_PL_SPI_ADDR1_18
set_location_assignment PIN_J2 -to CPLD_PL_SPI_ADDR2_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR0_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR1_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR2_18
set_location_assignment PIN_K1 -to CPLD_PL_SPI_LE_18
set_location_assignment PIN_H5 -to CPLD_PL_SPI_SCLK_18
set_location_assignment PIN_L3 -to CPLD_PL_SPI_SDI_18
set_location_assignment PIN_L2 -to CPLD_PL_SPI_SDO_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_LE_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SCLK_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SDI_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SDO_18
set_location_assignment PIN_M2 -to DAC_Alarm_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_Alarm_18
set_location_assignment PIN_N3 -to DAC_SPI_SDIO_18
set_location_assignment PIN_N2 -to DAC_SPI_SCLK_18
set_location_assignment PIN_M3 -to DAC_SPI_CS_L_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_CS_L_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_SCLK_18
set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_SDIO_18
set_location_assignment PIN_M7 -to LOSYNTH_RX_MUXOUT
set_location_assignment PIN_N7 -to LOSYNTH_TX_MUXOUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LOSYNTH_RX_MUXOUT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LOSYNTH_TX_MUXOUT
set_location_assignment PIN_E6 -to LO_RX_CS_L
set_location_assignment PIN_B2 -to LO_SPI_SCLK
set_location_assignment PIN_M4 -to LO_SPI_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_RX_CS_L
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_SPI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_SPI_SDI
set_location_assignment PIN_K5 -to LO_TX_CS_L
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_TX_CS_L
set_location_assignment PIN_B6 -to Rx_DSA1_LE
set_location_assignment PIN_A9 -to Rx_DSA2_LE
set_location_assignment PIN_D8 -to Rx_DSA_C1
set_location_assignment PIN_D6 -to Rx_DSA_C2
set_location_assignment PIN_A11 -to Rx_DSA_C4
set_location_assignment PIN_B10 -to Rx_DSA_C8
set_location_assignment PIN_A10 -to Rx_DSA_C16
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA1_LE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA2_LE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C4
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C8
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C16
set_location_assignment PIN_B3 -to Rx_Demod_ADJ_1
set_location_assignment PIN_N4 -to Rx_Demod_ADJ_2
set_location_assignment PIN_J5 -to Rx_LO_Filter_Sw_1
set_location_assignment PIN_J7 -to Rx_LO_Filter_Sw_2
set_location_assignment PIN_L4 -to Rx_LO_Input_Select
set_location_assignment PIN_A6 -to Rx_Sw1_Ctrl_1
set_location_assignment PIN_A7 -to Rx_Sw1_Ctrl_2
set_location_assignment PIN_A5 -to Rx_Sw2_Ctrl
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Demod_ADJ_1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Demod_ADJ_2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw1_Ctrl_1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw1_Ctrl_2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw2_Ctrl
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Filter_Sw_1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Filter_Sw_2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Input_Select
set_location_assignment PIN_A4 -to Rx_Sw3_Ctrl_1
set_location_assignment PIN_A3 -to Rx_Sw3_Ctrl_2
set_location_assignment PIN_C10 -to Rx_Sw4_Ctrl_1
set_location_assignment PIN_A8 -to Rx_Sw4_Ctrl_2
set_location_assignment PIN_B9 -to Rx_Sw4_Ctrl_3
set_location_assignment PIN_C9 -to Rx_Sw4_Ctrl_4
set_location_assignment PIN_K13 -to Tx_DSA1_LE
set_location_assignment PIN_K12 -to Tx_DSA2_LE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw3_Ctrl_1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw3_Ctrl_2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_3
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_4
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA1_LE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA2_LE
set_location_assignment PIN_H13 -to Tx_DSA_C1
set_location_assignment PIN_H8 -to Tx_DSA_C2
set_location_assignment PIN_J13 -to Tx_DSA_C4
set_location_assignment PIN_H10 -to Tx_DSA_C8
set_location_assignment PIN_J12 -to Tx_DSA_C16
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C4
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C8
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C16
set_location_assignment PIN_N6 -to Tx_LO_Filter_Sw_1
set_location_assignment PIN_N12 -to Tx_LO_Filter_Sw_2
set_location_assignment PIN_N8 -to Tx_LO_Input_Select
set_location_assignment PIN_L10 -to Tx_Sw1_Ctrl_1
set_location_assignment PIN_N10 -to Tx_Sw1_Ctrl_2
set_location_assignment PIN_N11 -to Tx_Sw2_Ctrl_1
set_location_assignment PIN_L11 -to Tx_Sw2_Ctrl_2
set_location_assignment PIN_L12 -to Tx_Sw3_Ctrl_1
set_location_assignment PIN_M13 -to Tx_Sw3_Ctrl_2
set_location_assignment PIN_K11 -to Tx_Sw3_Ctrl_3
set_location_assignment PIN_J9 -to Tx_Sw3_Ctrl_4
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Filter_Sw_1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Filter_Sw_2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Input_Select
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw1_Ctrl_1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw1_Ctrl_2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw2_Ctrl_1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw2_Ctrl_2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_3
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_4
set_location_assignment PIN_B11 -to PHDAC_SPI_CS_L
set_location_assignment PIN_C11 -to PHDAC_SPI_SCLK
set_location_assignment PIN_D9 -to PHDAC_SPI_SDI
set_location_assignment PIN_N9 -to LODIST_Bd_SPI_CS_L
set_location_assignment PIN_J8 -to LODIST_Bd_SPI_SCLK
set_location_assignment PIN_M9 -to LODIST_Bd_SPI_SDI
set_location_assignment PIN_L13 -to LO_DSA_C1
set_location_assignment PIN_K10 -to LO_DSA_C2
set_location_assignment PIN_H9 -to LO_DSA_C4
set_location_assignment PIN_G12 -to LO_DSA_C8
set_location_assignment PIN_G13 -to LO_DSA_C16
set_location_assignment PIN_J10 -to RxLO_DSA_LE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_CS_L
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C4
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C8
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C16
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RxLO_DSA_LE
set_location_assignment PIN_B4 -to Rx_Sw6_Ctrl_1
set_location_assignment PIN_B5 -to Rx_Sw6_Ctrl_2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw6_Ctrl_1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw6_Ctrl_2
set_location_assignment PIN_M8 -to TxLO_DSA_LE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TxLO_DSA_LE
set_location_assignment PIN_M11 -to Tx_Sw5_Ctrl_1
set_location_assignment PIN_M12 -to Tx_Sw5_Ctrl_2
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw5_Ctrl_1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw5_Ctrl_2
set_location_assignment PIN_D12 -to Cal_iso_Sw_Ctrl
set_location_assignment PIN_K8 -to LODIST_Bd_IO1
set_location_assignment PIN_M10 -to Tx_HB_LB_Select
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_HB_LB_Select
set_location_assignment PIN_E8 -to Rx_HB_LB_Select
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_HB_LB_Select
set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_CS_L
set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_SCLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_SDI
set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_ADDR0_25
set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_ADDR1_25
set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_CLK_25
set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_LE_25
set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_SDI_25
set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_SDO_25
set_instance_assignment -name IO_STANDARD "2.5 V" -to Cal_iso_Sw_Ctrl
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to LODIST_Bd_IO1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_location_assignment PIN_E4 -to usrp_io[0]
set_location_assignment PIN_G5 -to usrp_io[1]
set_location_assignment PIN_H4 -to usrp_io[2]
set_location_assignment PIN_J1 -to usrp_io[3]
set_location_assignment PIN_F1 -to usrp_io[4]
set_location_assignment PIN_C12 -to usrp_io[5]
set_location_assignment PIN_C13 -to usrp_io[6]
set_location_assignment PIN_E12 -to usrp_io[7]
set_location_assignment PIN_E13 -to usrp_io[8]
set_location_assignment PIN_B13 -to usrp_io[9]
set_location_assignment PIN_F9 -to usrp_io[10]
set_location_assignment PIN_B12 -to usrp_io[11]
set_location_assignment PIN_E9 -to usrp_io[12]
set_location_assignment PIN_F8 -to usrp_io[13]
set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[12]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[13]
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH rh_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME rh_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id rh_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "9000 ns" -section_id rh_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME rh_tb -section_id rh_tb
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name VERILOG_FILE rhodium_top.v
set_global_assignment -name VERILOG_FILE rhodium_gain_ctrl.v
set_global_assignment -name VERILOG_FILE rhodium_gain_table.v
set_global_assignment -name VERILOG_FILE rhodium_lo_gain.v
set_global_assignment -name VERILOG_FILE rh_tb.v
set_global_assignment -name EDA_TEST_BENCH_FILE rh_tb.v -section_id rh_tb
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name GENERATE_SVF_FILE ON
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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