7e59e9516d
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Original-commit: 7015f5ed2d495f3908773b7c7d74864d0cc3871a
94 lines
2.5 KiB
Verilog
94 lines
2.5 KiB
Verilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: reset_generator
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//
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// Description:
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//
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// Generates a power-on reset signal that is asserted at startup and stays
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// asserted for at least CYCLES_IN_RESET clock cycles.
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//
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// Internally, it generates a 1-bit synchronous signal (initialize) to safely
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// initialize the power_on_reset_counter incremental counter to 0's.
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//
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// A delayed version of the initializing signal is also generated
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// (counter_enable) to start counting.
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//
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// 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_ 9_
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// clk _| |_| |_| |_| |_| |_| |_| |_| |_|
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// _____________________
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// initialize _____________|
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// _________
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// counter_enable _________________________|
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//
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`default_nettype none
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module reset_generator (
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input wire clk,
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output reg power_on_reset = 1'b1
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);
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wire [0:0] counter_enable;
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wire [0:0] initialize;
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synchronizer #(
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.WIDTH (1),
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.STAGES (3),
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.INITIAL_VAL (1'b0),
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.FALSE_PATH_TO_IN (0)
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) init_sync_inst (
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.clk (clk),
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.rst (1'b0),
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.in (1'b1),
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.out (initialize)
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);
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synchronizer #(
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.WIDTH (1),
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.STAGES (3),
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.INITIAL_VAL (1'b0),
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.FALSE_PATH_TO_IN (0)
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) counter_en_sync_inst (
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.clk (clk),
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.rst (1'b0),
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.in (initialize),
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.out (counter_enable)
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);
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// Internal synchronous reset generator.
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localparam CYCLES_IN_RESET = 20;
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reg [7:0] power_on_reset_counter = 8'b0;
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// This block generates a synchronous reset in the clk domain that can be
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// used by downstream logic.
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//
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// power_on_reset_counter is first initialized to 0's upon assertion of
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// initialize. Some cycles later (3), upon assertion if counter_enable,
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// power_on_reset_counter starts to increment.
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//
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// power_on_reset will remain asserted until power_on_reset_counter reaches
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// cycles_in_reset, resulting in the deassertion of power_on_reset.
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always @(posedge clk) begin : power_on_reset_gen
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if (counter_enable) begin
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if (power_on_reset_counter == CYCLES_IN_RESET-1) begin
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power_on_reset <= 1'b0;
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end else begin
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power_on_reset_counter <= power_on_reset_counter + 1'b1;
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power_on_reset <= 1'b1;
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end
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end
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else if (initialize) begin
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power_on_reset_counter <= 8'b0;
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power_on_reset <= 1'b1;
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end
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end
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endmodule
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`default_nettype wire
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