miegl/b210-k7-fpga
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b210-k7-fpga/tools/scripts
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Javier Valenzuela 9513397e17 fpga: tools: Lattice build flow clean-up 
Original-commit: fd2dd921a2af4bff1a26c43385b3942bc143f934
2022-08-03 14:28:21 -05:00
..
check_config.json
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dmd_design_build.tcl
fpga: tools: Lattice build flow clean-up
2022-08-03 14:28:21 -05:00
git-hash.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ise_jtag_program.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
launch_modelsim.sh
fpga: tools: Detect assertions in ModelSim simulation
2021-06-17 08:16:59 -05:00
launch_vivado.py
fpga: Remove Python2 support from build system
2021-01-04 13:28:36 -06:00
launch_vivado.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
launch_vlint.sh
fpga: tools: Put SIM_SRCS at end of compile order
2021-06-17 08:16:59 -05:00
setupenv_base.sh
fpga: tools: Update Vivado scripts to use python3
2021-12-08 12:07:36 -08:00
shared-ip-loc-manage.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_check_syntax.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_gen_ip_makefile.py
fpga: Remove Python2 support from build system
2021-01-04 13:28:36 -06:00
viv_gen_part_id.py
fpga: Remove Python2 support from build system
2021-01-04 13:28:36 -06:00
viv_generate_bd.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_generate_hls_ip.tcl
fpga: hls: Add version to generated HLS IP
2022-01-13 14:33:59 -06:00
viv_generate_ip.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_generate_patch_ip.tcl
fpga: tools: Add ability to patch IP during generation
2021-06-03 10:22:04 -05:00
viv_hardware_utils.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_ip_utils.tcl
fpga: tools: Ignore BD layout info for TCL-based BD
2020-03-12 10:33:24 -05:00
viv_ip_xci_editor.py
fpga: tools: Add support for RFSoC
2021-06-03 10:22:04 -05:00
viv_sim_project.tcl
fpga: tools: Add UHD_FPGA_DIR definition to synthesis
2021-09-08 08:36:05 -05:00
viv_strategies.tcl
fpga: tools: Add ability to run commands before route
2021-06-03 10:22:04 -05:00
viv_synth.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_utils.tcl
fpga: tools: Fix adding directories for HDL source
2022-01-13 14:33:59 -06:00
xil_bitfile_parser.py
fpga: Fix Xilinx bitfile parser for Python 3
2021-08-24 09:45:36 -05:00