Wade Fife
40c76b8d9a
Per the RFNoC specification, if we set the frequency of flow control updates to 0 then the input stream will not send flow control status updates to the output stream handler. This change makes it so that when the frequency of flow control status updates is configured to be zero in the FPGA output stream handler (i.e., cfg_fc_freq_bytes and cfg_fc_freq_pkts are both 0 in chdr_stream_output) then the output stream handler will not use flow control. That is, chdr_stream_output will not expect stream status updates and will not restrict output packets. Original-commit: 184999c54f0f30a7952d4e8560b393730c00e353
626 lines
26 KiB
Verilog
626 lines
26 KiB
Verilog
//
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// Copyright 2018-2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: chdr_stream_endpoint
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// Description:
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// The implementation of a stream endpoint. This module serves as
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// an endpoint for a bidirectional stream. It implement a control
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// and a data path, both of which can be individually enabled using
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// parameters. The control path contains a bidirectional CHDR to
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// AXIS-Control converter. The data path has a stream input and
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// output port.
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//
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// Parameters:
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// - PROTOVER: RFNoC protocol version {8'd<major>, 8'd<minor>}
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// - CHDR_W: Width of the CHDR bus in bits
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// - INST_NUM: The instance number of this module
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// - CTRL_XBAR_PORT: The port index on the control crossbar that
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// this module's control path will connect to
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// - AXIS_CTRL_EN: Enable control traffic (axis_ctrl port)
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// - AXIS_DATA_EN: Enable data traffic (axis_data port)
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// - NUM_DATA_I: Number of AXIS data slave ports
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// - NUM_DATA_O: Number of AXIS data master ports
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// - INGRESS_BUFF_SIZE: Buffer size in log2 of the number of words
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// in the ingress buffer for the stream
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// - MTU: Log2 of the maximum packet size in words
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// - REPORT_STRM_ERRS: Report data stream errors upstream
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// - SIM_SPEEDUP: Set to 1 in simultion, and 0 otherwise
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//
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// Signals:
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// - device_id : The ID of the device that has instantiated this module
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// - *_axis_chdr_* : Input/output CHDR stream (AXI-Stream)
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// - *_axis_ctrl_* : Input/output AXIS-Control streams (AXI-Stream)
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// - *_axis_data_* : Input/output CHDR Data streams (AXI-Stream)
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// - strm_*_err_stb: The stream encountered an error
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// - signal_*_err : Notify upstream that we encountered an error
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module chdr_stream_endpoint #(
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parameter [15:0] PROTOVER = {8'd1, 8'd0},
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parameter CHDR_W = 64,
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parameter [9:0] INST_NUM = 0,
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parameter [9:0] CTRL_XBAR_PORT = 0,
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parameter [0:0] AXIS_CTRL_EN = 1,
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parameter [0:0] AXIS_DATA_EN = 1,
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parameter [5:0] NUM_DATA_I = 1,
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parameter [5:0] NUM_DATA_O = 1,
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parameter [5:0] INGRESS_BUFF_SIZE = 12,
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parameter [5:0] MTU = 10,
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parameter [0:0] REPORT_STRM_ERRS = 1,
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parameter [0:0] SIM_SPEEDUP = 0
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)(
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// Clock, reset and settings
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input wire rfnoc_chdr_clk,
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input wire rfnoc_chdr_rst,
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input wire rfnoc_ctrl_clk,
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input wire rfnoc_ctrl_rst,
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// Device info
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input wire [15:0] device_id,
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// CHDR in (AXI-Stream)
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input wire [CHDR_W-1:0] s_axis_chdr_tdata,
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input wire s_axis_chdr_tlast,
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input wire s_axis_chdr_tvalid,
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output wire s_axis_chdr_tready,
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// CHDR out (AXI-Stream)
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output wire [CHDR_W-1:0] m_axis_chdr_tdata,
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output wire m_axis_chdr_tlast,
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output wire m_axis_chdr_tvalid,
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input wire m_axis_chdr_tready,
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// Flow controlled data in (AXI-Stream)
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input wire [(CHDR_W*NUM_DATA_I)-1:0] s_axis_data_tdata,
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input wire [NUM_DATA_I-1:0] s_axis_data_tlast,
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input wire [NUM_DATA_I-1:0] s_axis_data_tvalid,
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output wire [NUM_DATA_I-1:0] s_axis_data_tready,
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// Flow controlled data out (AXI-Stream)
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output wire [(CHDR_W*NUM_DATA_O)-1:0] m_axis_data_tdata,
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output wire [NUM_DATA_O-1:0] m_axis_data_tlast,
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output wire [NUM_DATA_O-1:0] m_axis_data_tvalid,
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input wire [NUM_DATA_O-1:0] m_axis_data_tready,
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// Control in (AXI-Stream)
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input wire [31:0] s_axis_ctrl_tdata,
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input wire s_axis_ctrl_tlast,
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input wire s_axis_ctrl_tvalid,
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output wire s_axis_ctrl_tready,
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// Control out (AXI-Stream)
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output wire [31:0] m_axis_ctrl_tdata,
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output wire m_axis_ctrl_tlast,
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output wire m_axis_ctrl_tvalid,
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input wire m_axis_ctrl_tready,
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// Stream status specfic
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output wire strm_seq_err_stb,
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output wire strm_data_err_stb,
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output wire strm_route_err_stb,
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input wire signal_data_err
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);
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// ---------------------------------------------------
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// RFNoC Includes
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// ---------------------------------------------------
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`include "rfnoc_chdr_utils.vh"
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`include "rfnoc_chdr_internal_utils.vh"
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// ---------------------------------------------------
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// Filter packets by type
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// ---------------------------------------------------
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wire [CHDR_W-1:0] ctrl_i_tdata, ctrl_o_tdata;
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wire ctrl_i_tlast, ctrl_o_tlast;
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wire ctrl_i_tvalid, ctrl_o_tvalid;
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wire ctrl_i_tready, ctrl_o_tready;
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wire [CHDR_W-1:0] data_i_tdata, data_o_tdata;
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wire data_i_tlast, data_o_tlast;
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wire data_i_tvalid, data_o_tvalid;
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wire data_i_tready, data_o_tready;
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wire [CHDR_W-1:0] strs_i_tdata, strs_o_tdata;
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wire strs_i_tlast, strs_o_tlast;
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wire strs_i_tvalid, strs_o_tvalid;
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wire strs_i_tready, strs_o_tready;
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wire [CHDR_W-1:0] mgmt_i_tdata, mgmt_o_tdata;
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wire mgmt_i_tlast, mgmt_o_tlast;
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wire mgmt_i_tvalid, mgmt_o_tvalid;
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wire mgmt_i_tready, mgmt_o_tready;
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function [1:0] compute_demux_dest;
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input [63:0] hdr;
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if (chdr_get_pkt_type(hdr) == CHDR_PKT_TYPE_CTRL)
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// Control
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compute_demux_dest = 2'd2;
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else if (chdr_get_pkt_type(hdr) == CHDR_PKT_TYPE_STRC ||
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chdr_get_pkt_type(hdr) == CHDR_PKT_TYPE_DATA ||
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chdr_get_pkt_type(hdr) == CHDR_PKT_TYPE_DATA_TS)
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// Data and stream command
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compute_demux_dest = 2'd1;
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else if (chdr_get_pkt_type(hdr) == CHDR_PKT_TYPE_STRS)
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// Stream status
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compute_demux_dest = 2'd0;
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else
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// Management (all packets must return to sender)
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compute_demux_dest = 2'd3;
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endfunction
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// We give the demux a FIFO large enough to buffer short packets
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// Flow control will ensure that data does not back up through
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// this demux but we might have the other packet types block
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// each other.
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localparam DEMUX_FIFO_SIZE = 5;
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wire [CHDR_W-1:0] chdr_header;
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axi_demux #(
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.WIDTH(CHDR_W), .SIZE(4), .PRE_FIFO_SIZE(DEMUX_FIFO_SIZE), .POST_FIFO_SIZE(1)
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) mgmt_demux_i (
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.clk(rfnoc_chdr_clk), .reset(rfnoc_chdr_rst), .clear(1'b0),
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.header(chdr_header), .dest(compute_demux_dest(chdr_header[63:0])),
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.i_tdata (s_axis_chdr_tdata ),
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.i_tlast (s_axis_chdr_tlast ),
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.i_tvalid(s_axis_chdr_tvalid),
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.i_tready(s_axis_chdr_tready),
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.o_tdata ({mgmt_i_tdata, ctrl_i_tdata, data_i_tdata, strs_i_tdata }),
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.o_tlast ({mgmt_i_tlast, ctrl_i_tlast, data_i_tlast, strs_i_tlast }),
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.o_tvalid({mgmt_i_tvalid, ctrl_i_tvalid, data_i_tvalid, strs_i_tvalid}),
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.o_tready({mgmt_i_tready, ctrl_i_tready, data_i_tready, strs_i_tready})
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);
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axi_mux #(
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.WIDTH(CHDR_W), .SIZE(4), .PRIO(1), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
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) mgmt_mux_i (
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.clk(rfnoc_chdr_clk), .reset(rfnoc_chdr_rst), .clear(1'b0),
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.i_tdata ({mgmt_o_tdata, data_o_tdata, strs_o_tdata, ctrl_o_tdata }),
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.i_tlast ({mgmt_o_tlast, data_o_tlast, strs_o_tlast, ctrl_o_tlast }),
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.i_tvalid({mgmt_o_tvalid, data_o_tvalid, strs_o_tvalid, ctrl_o_tvalid}),
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.i_tready({mgmt_o_tready, data_o_tready, strs_o_tready, ctrl_o_tready}),
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.o_tdata (m_axis_chdr_tdata ),
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.o_tlast (m_axis_chdr_tlast ),
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.o_tvalid(m_axis_chdr_tvalid),
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.o_tready(m_axis_chdr_tready)
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);
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// ---------------------------------------------------
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// Management Path
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// ---------------------------------------------------
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wire ctrlport_req_wr, ctrlport_req_rd;
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reg ctrlport_resp_ack = 1'b0;
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wire [15:0] ctrlport_req_addr;
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wire [31:0] ctrlport_req_data;
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reg [31:0] ctrlport_resp_data;
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localparam [17:0] EXTENDED_INFO = {
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3'b0, REPORT_STRM_ERRS, NUM_DATA_O, NUM_DATA_I, AXIS_DATA_EN, AXIS_CTRL_EN};
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// Handle management packets here
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chdr_mgmt_pkt_handler #(
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.PROTOVER(PROTOVER), .CHDR_W(CHDR_W), .MGMT_ONLY(1)
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) mgmt_ep_i (
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.clk(rfnoc_chdr_clk), .rst(rfnoc_chdr_rst),
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.node_info(chdr_mgmt_build_node_info(EXTENDED_INFO, INST_NUM, NODE_TYPE_STREAM_EP, device_id)),
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.s_axis_chdr_tdata(mgmt_i_tdata), .s_axis_chdr_tlast(mgmt_i_tlast),
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.s_axis_chdr_tvalid(mgmt_i_tvalid), .s_axis_chdr_tready(mgmt_i_tready),
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.s_axis_chdr_tuser(1'd0),
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.m_axis_chdr_tdata(mgmt_o_tdata), .m_axis_chdr_tlast(mgmt_o_tlast),
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.m_axis_chdr_tdest(/* unused */), .m_axis_chdr_tid(/* unused */),
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.m_axis_chdr_tvalid(mgmt_o_tvalid), .m_axis_chdr_tready(mgmt_o_tready),
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.ctrlport_req_wr(ctrlport_req_wr), .ctrlport_req_rd(ctrlport_req_rd),
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.ctrlport_req_addr(ctrlport_req_addr), .ctrlport_req_data(ctrlport_req_data),
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.ctrlport_resp_ack(ctrlport_resp_ack), .ctrlport_resp_data(ctrlport_resp_data),
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.op_stb(/* unused */), .op_dst_epid(/* unused */), .op_src_epid(/* unused */),
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.op_data(/* unused */)
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);
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// ============================== REGISTERS ==============================
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// * REG_EPID_SELF (Read-Write):
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// The endpoint ID of this stream endpoint
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// - [15:0]: Endpoint ID
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// * REG_RESET_AND_FLUSH (Write-Only):
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// Reset and flush register
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// - [0]: Flush data path
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// - [1]: Flush control path
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// * REG_OSTRM_CTRL_STATUS (Read-Write):
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// Control and status register for the output stream
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// - [0] : Configuration start (strobe)
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// - [1] : Is this transport lossy?
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// - [3:2] : Payload SW buff (0=u64, 1=u32, 2=u16, 3=u8)
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// - [5:4] : Metadata SW buff (0=u64, 1=u32, 2=u16, 3=u8)
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// - [6] : Swap endianness
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// - [28:7]: <Unused>
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// - [29] : Configuration is pending (read-only)
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// - [30] : Configuration has failed (read-only)
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// - [31] : Is flow-control enabled? (read-only)
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// * REG_OSTRM_DST_EPID (Write-Only):
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// The endpoint ID of a downstream stream endpoint
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// - [15:0]: Endpoint ID
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// * REG_OSTRM_FC_FREQ_BYTES_LO, REG_OSTRM_FC_FREQ_BYTES_HI (Write-Only):
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// Number of bytes between flow control status messages
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// * REG_OSTRM_FC_FREQ_PKTS (Write-Only):
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// Number of packets between flow control status messages
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// * REG_OSTRM_FC_HEADROOM (Write-Only):
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// Flow control headroom register
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// - [15:0]: Bytes of headroom
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// - [23:16]: Packets of headroom
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// * REG_OSTRM_BUFF_CAP_BYTES_LO, REG_OSTRM_BUFF_CAP_BYTES_HI (Read-Only):
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// Number of bytes in the downstream buffer
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// * REG_OSTRM_BUFF_CAP_PKTS (Read-Only):
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// Number of packets in the downstream buffer
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// * REG_OSTRM_SEQ_ERR_CNT (Read-Only):
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// Number of sequence errors since initialization
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// * REG_OSTRM_DATA_ERR_CNT (Read-Only):
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// Number of data integrity errors since initialization
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// * REG_OSTRM_ROUTE_ERR_CNT (Read-Only):
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// Number of routing errors since initialization
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// * REG_ISTRM_CTRL_STATUS (Read-Write):
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// Control and status register for the input stream
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// - [0] : Reserved
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// - [1] : Reserved
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// - [3:2]: Payload SW buff (0=u64, 1=u32, 2=u16, 3=u8)
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// - [5:4]: Metadata SW buff (0=u64, 1=u32, 2=u16, 3=u8)
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// - [6] : Swap endianness
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// =======================================================================
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localparam [15:0] REG_EPID_SELF = 16'h00; //RW
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localparam [15:0] REG_RESET_AND_FLUSH = 16'h04; //W
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localparam [15:0] REG_OSTRM_CTRL_STATUS = 16'h08; //RW
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localparam [15:0] REG_OSTRM_DST_EPID = 16'h0C; //W
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localparam [15:0] REG_OSTRM_FC_FREQ_BYTES_LO = 16'h10; //W
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localparam [15:0] REG_OSTRM_FC_FREQ_BYTES_HI = 16'h14; //W
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localparam [15:0] REG_OSTRM_FC_FREQ_PKTS = 16'h18; //W
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localparam [15:0] REG_OSTRM_FC_HEADROOM = 16'h1C; //W
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localparam [15:0] REG_OSTRM_BUFF_CAP_BYTES_LO = 16'h20; //R
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localparam [15:0] REG_OSTRM_BUFF_CAP_BYTES_HI = 16'h24; //R
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localparam [15:0] REG_OSTRM_BUFF_CAP_PKTS = 16'h28; //R
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localparam [15:0] REG_OSTRM_SEQ_ERR_CNT = 16'h2C; //R
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localparam [15:0] REG_OSTRM_DATA_ERR_CNT = 16'h30; //R
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localparam [15:0] REG_OSTRM_ROUTE_ERR_CNT = 16'h34; //R
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localparam [15:0] REG_ISTRM_CTRL_STATUS = 16'h38; //RW
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// Configurable registers
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reg [15:0] reg_epid_self = 16'h0;
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reg reg_ctrl_reset = 1'b0;
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reg reg_istrm_reset = 1'b0;
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reg reg_ostrm_reset = 1'b0;
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reg reg_ostrm_cfg_start = 1'b0;
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wire reg_ostrm_cfg_pending;
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wire reg_ostrm_cfg_failed;
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reg reg_ostrm_cfg_lossy_xport = 1'b0;
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reg [1:0] reg_ostrm_cfg_pyld_sw_buff = 2'd0;
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reg [1:0] reg_ostrm_cfg_mdata_sw_buff = 2'd0;
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reg reg_ostrm_cfg_swap_endian = 1'b0;
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reg [15:0] reg_ostrm_dst_epid = 16'h0;
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reg [39:0] reg_fc_freq_bytes = 40'h0;
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reg [23:0] reg_fc_freq_pkts = 24'h0;
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reg [15:0] reg_fc_headroom_bytes = 16'd0;
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reg [7:0] reg_fc_headroom_pkts = 8'd0;
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reg [1:0] reg_istrm_cfg_pyld_sw_buff = 2'd0;
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reg [1:0] reg_istrm_cfg_mdata_sw_buff = 2'd0;
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reg reg_istrm_cfg_swap_endian = 1'b0;
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wire reg_fc_enabled;
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wire [39:0] reg_buff_cap_bytes;
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wire [23:0] reg_buff_cap_pkts;
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wire [31:0] reg_seq_err_cnt;
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wire [31:0] reg_data_err_cnt;
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wire [31:0] reg_route_err_cnt;
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always @(posedge rfnoc_chdr_clk) begin
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if (rfnoc_chdr_rst) begin
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ctrlport_resp_ack <= 1'b0;
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end else begin
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// All transactions finish in 1 cycle
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ctrlport_resp_ack <= ctrlport_req_wr | ctrlport_req_rd;
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// Handle register writes
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if (ctrlport_req_wr) begin
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case(ctrlport_req_addr)
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REG_EPID_SELF:
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reg_epid_self <= ctrlport_req_data[15:0];
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REG_RESET_AND_FLUSH:
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{reg_ctrl_reset, reg_istrm_reset, reg_ostrm_reset} <= ctrlport_req_data[2:0];
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REG_OSTRM_CTRL_STATUS:
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{reg_ostrm_cfg_swap_endian, reg_ostrm_cfg_mdata_sw_buff, reg_ostrm_cfg_pyld_sw_buff,
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reg_ostrm_cfg_lossy_xport, reg_ostrm_cfg_start} <= ctrlport_req_data[6:0];
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REG_OSTRM_DST_EPID:
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reg_ostrm_dst_epid <= ctrlport_req_data[15:0];
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REG_OSTRM_FC_FREQ_BYTES_LO:
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reg_fc_freq_bytes[31:0] <= ctrlport_req_data[31:0];
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REG_OSTRM_FC_FREQ_BYTES_HI:
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reg_fc_freq_bytes[39:32] <= ctrlport_req_data[7:0];
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REG_OSTRM_FC_FREQ_PKTS:
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reg_fc_freq_pkts <= ctrlport_req_data[23:0];
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REG_OSTRM_FC_HEADROOM:
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{reg_fc_headroom_pkts, reg_fc_headroom_bytes} <= ctrlport_req_data[23:0];
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REG_ISTRM_CTRL_STATUS:
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{reg_istrm_cfg_swap_endian, reg_istrm_cfg_mdata_sw_buff, reg_istrm_cfg_pyld_sw_buff}
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<= ctrlport_req_data[6:2];
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endcase
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end else begin
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// Strobed registers
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reg_ostrm_cfg_start <= 1'b0;
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reg_ctrl_reset <= 1'b0;
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reg_ostrm_reset <= 1'b0;
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reg_istrm_reset <= 1'b0;
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end
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// Handle register reads
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if (ctrlport_req_rd) begin
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case(ctrlport_req_addr)
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REG_EPID_SELF:
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ctrlport_resp_data <= {16'h0, reg_epid_self};
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REG_OSTRM_CTRL_STATUS:
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ctrlport_resp_data <= {
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reg_fc_enabled, reg_ostrm_cfg_failed, reg_ostrm_cfg_pending, 23'h0,
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reg_ostrm_cfg_mdata_sw_buff, reg_ostrm_cfg_pyld_sw_buff,
|
|
reg_ostrm_cfg_lossy_xport, 1'b0};
|
|
REG_OSTRM_BUFF_CAP_BYTES_LO:
|
|
ctrlport_resp_data <= reg_buff_cap_bytes[31:0];
|
|
REG_OSTRM_BUFF_CAP_BYTES_HI:
|
|
ctrlport_resp_data <= {24'h0, reg_buff_cap_bytes[39:32]};
|
|
REG_OSTRM_BUFF_CAP_PKTS:
|
|
ctrlport_resp_data <= {8'h0, reg_buff_cap_pkts};
|
|
REG_OSTRM_SEQ_ERR_CNT:
|
|
ctrlport_resp_data <= reg_seq_err_cnt;
|
|
REG_OSTRM_DATA_ERR_CNT:
|
|
ctrlport_resp_data <= reg_data_err_cnt;
|
|
REG_OSTRM_ROUTE_ERR_CNT:
|
|
ctrlport_resp_data <= reg_route_err_cnt;
|
|
REG_ISTRM_CTRL_STATUS:
|
|
ctrlport_resp_data <= {26'h0,
|
|
reg_istrm_cfg_mdata_sw_buff, reg_istrm_cfg_pyld_sw_buff, 2'b0};
|
|
default:
|
|
ctrlport_resp_data <= 32'h0;
|
|
endcase
|
|
end
|
|
end
|
|
end
|
|
|
|
// ---------------------------------------------------
|
|
// Data and Flow Control Path
|
|
// ---------------------------------------------------
|
|
genvar i;
|
|
generate if (AXIS_DATA_EN) begin: datapath
|
|
localparam INPUT_FLUSH_TIMEOUT_W = SIM_SPEEDUP ? 6 : 14;
|
|
|
|
// Data => CHDR
|
|
//-------------
|
|
wire [CHDR_W-1:0] axis_di_tdata, axis_dis_tdata, axis_di_tdata_pre;
|
|
wire [5:0] axis_di_tdest;
|
|
wire axis_di_tlast, axis_dis_tlast;
|
|
wire axis_di_tvalid, axis_dis_tvalid;
|
|
wire axis_di_tready, axis_dis_tready;
|
|
|
|
// Optional MUX to combine multiple input data ports into a single one
|
|
if (NUM_DATA_I == 6'd1) begin
|
|
axi_fifo #(.WIDTH(CHDR_W+1), .SIZE(1)) axis_s_reg_i (
|
|
.clk(rfnoc_chdr_clk), .reset(rfnoc_chdr_rst | reg_ostrm_reset), .clear(1'b0),
|
|
.i_tdata({s_axis_data_tlast, s_axis_data_tdata}),
|
|
.i_tvalid(s_axis_data_tvalid), .i_tready(s_axis_data_tready),
|
|
.o_tdata({axis_di_tlast, axis_di_tdata_pre}),
|
|
.o_tvalid(axis_di_tvalid), .o_tready(axis_di_tready),
|
|
.space(), .occupied()
|
|
);
|
|
assign axis_di_tdest = 6'd0;
|
|
end else begin
|
|
wire [((CHDR_W+6)*NUM_DATA_I)-1:0] s_axis_data_tdata_tmp;
|
|
for (i = 0; i < NUM_DATA_I; i=i+1) begin
|
|
assign s_axis_data_tdata_tmp[(i*(CHDR_W+6))+:(CHDR_W+6)] = {i[5:0], s_axis_data_tdata[(i*CHDR_W)+:CHDR_W]};
|
|
end
|
|
|
|
axi_mux #(
|
|
.WIDTH(CHDR_W+6), .SIZE(NUM_DATA_I), .PRIO(0), .PRE_FIFO_SIZE(1), .POST_FIFO_SIZE(1)
|
|
) axis_s_mux_i (
|
|
.clk(rfnoc_chdr_clk), .reset(rfnoc_chdr_rst | reg_ostrm_reset), .clear(1'b0),
|
|
.i_tdata(s_axis_data_tdata_tmp), .i_tlast(s_axis_data_tlast),
|
|
.i_tvalid(s_axis_data_tvalid), .i_tready(s_axis_data_tready),
|
|
.o_tdata({axis_di_tdest, axis_di_tdata_pre}), .o_tlast(axis_di_tlast),
|
|
.o_tvalid(axis_di_tvalid), .o_tready(axis_di_tready)
|
|
);
|
|
end
|
|
|
|
// Logic to correctly fill in the VC field in the CHDR header
|
|
reg axis_di_hdr = 1'b1;
|
|
always @(posedge rfnoc_chdr_clk) begin
|
|
if (rfnoc_chdr_rst | reg_ostrm_reset)
|
|
axis_di_hdr <= 1'b1;
|
|
else if (axis_di_tvalid && axis_di_tready)
|
|
axis_di_hdr <= axis_di_tlast;
|
|
end
|
|
assign axis_di_tdata[63:0] = axis_di_hdr ? chdr_set_vc(axis_di_tdata_pre[63:0], axis_di_tdest) :
|
|
axis_di_tdata_pre[63:0];
|
|
if (CHDR_W > 64) begin
|
|
assign axis_di_tdata[CHDR_W-1:64] = axis_di_tdata_pre[CHDR_W-1:64];
|
|
end
|
|
|
|
// Module to swap words in the payload and metadata depending on SW settings
|
|
chdr_data_swapper #( .CHDR_W(CHDR_W)) di_swap_i (
|
|
.clk (rfnoc_chdr_clk),
|
|
.rst (rfnoc_chdr_rst | reg_ostrm_reset),
|
|
.payload_sw_buff(reg_ostrm_cfg_pyld_sw_buff),
|
|
.mdata_sw_buff (reg_ostrm_cfg_mdata_sw_buff),
|
|
.swap_endianness(reg_ostrm_cfg_swap_endian),
|
|
.s_axis_tdata (axis_di_tdata),
|
|
.s_axis_tlast (axis_di_tlast),
|
|
.s_axis_tvalid (axis_di_tvalid),
|
|
.s_axis_tready (axis_di_tready),
|
|
.m_axis_tdata (axis_dis_tdata),
|
|
.m_axis_tlast (axis_dis_tlast),
|
|
.m_axis_tvalid (axis_dis_tvalid),
|
|
.m_axis_tready (axis_dis_tready)
|
|
);
|
|
|
|
// Stream endpoint flow-control output module
|
|
chdr_stream_output #(
|
|
.CHDR_W(CHDR_W), .MTU(MTU)
|
|
) strm_output_i (
|
|
.clk (rfnoc_chdr_clk),
|
|
.rst (rfnoc_chdr_rst | reg_ostrm_reset),
|
|
.m_axis_chdr_tdata (data_o_tdata),
|
|
.m_axis_chdr_tlast (data_o_tlast),
|
|
.m_axis_chdr_tvalid (data_o_tvalid),
|
|
.m_axis_chdr_tready (data_o_tready),
|
|
.s_axis_data_tdata (axis_dis_tdata),
|
|
.s_axis_data_tlast (axis_dis_tlast),
|
|
.s_axis_data_tvalid (axis_dis_tvalid),
|
|
.s_axis_data_tready (axis_dis_tready),
|
|
.s_axis_strs_tdata (strs_i_tdata),
|
|
.s_axis_strs_tlast (strs_i_tlast),
|
|
.s_axis_strs_tvalid (strs_i_tvalid),
|
|
.s_axis_strs_tready (strs_i_tready),
|
|
.cfg_start (reg_ostrm_cfg_start),
|
|
.cfg_pending (reg_ostrm_cfg_pending),
|
|
.cfg_failed (reg_ostrm_cfg_failed),
|
|
.cfg_lossy_xport (reg_ostrm_cfg_lossy_xport),
|
|
.cfg_dst_epid (reg_ostrm_dst_epid),
|
|
.cfg_this_epid (reg_epid_self),
|
|
.cfg_fc_freq_bytes (reg_fc_freq_bytes),
|
|
.cfg_fc_freq_pkts (reg_fc_freq_pkts),
|
|
.cfg_fc_headroom_bytes(reg_fc_headroom_bytes),
|
|
.cfg_fc_headroom_pkts (reg_fc_headroom_pkts),
|
|
.fc_enabled (reg_fc_enabled),
|
|
.capacity_bytes (reg_buff_cap_bytes),
|
|
.capacity_pkts (reg_buff_cap_pkts),
|
|
.seq_err_stb (strm_seq_err_stb),
|
|
.seq_err_cnt (reg_seq_err_cnt),
|
|
.data_err_stb (strm_data_err_stb),
|
|
.data_err_cnt (reg_data_err_cnt),
|
|
.route_err_stb (strm_route_err_stb),
|
|
.route_err_cnt (reg_route_err_cnt)
|
|
);
|
|
|
|
// CHDR => Data
|
|
//-------------
|
|
wire [CHDR_W-1:0] axis_do_tdata, axis_dos_tdata;
|
|
wire axis_do_tlast, axis_dos_tlast;
|
|
wire axis_do_tvalid, axis_dos_tvalid;
|
|
wire axis_do_tready, axis_dos_tready;
|
|
|
|
// Stream endpoint flow-control input module
|
|
chdr_stream_input #(
|
|
.CHDR_W(CHDR_W), .BUFF_SIZE(INGRESS_BUFF_SIZE),
|
|
.FLUSH_TIMEOUT_W(INPUT_FLUSH_TIMEOUT_W),
|
|
.MONITOR_EN(0), .SIGNAL_ERRS(REPORT_STRM_ERRS)
|
|
) strm_input_i (
|
|
.clk (rfnoc_chdr_clk),
|
|
.rst (rfnoc_chdr_rst | reg_istrm_reset),
|
|
.s_axis_chdr_tdata (data_i_tdata),
|
|
.s_axis_chdr_tlast (data_i_tlast),
|
|
.s_axis_chdr_tvalid(data_i_tvalid),
|
|
.s_axis_chdr_tready(data_i_tready),
|
|
.m_axis_data_tdata (axis_do_tdata),
|
|
.m_axis_data_tlast (axis_do_tlast),
|
|
.m_axis_data_tvalid(axis_do_tvalid),
|
|
.m_axis_data_tready(axis_do_tready),
|
|
.m_axis_strs_tdata (strs_o_tdata),
|
|
.m_axis_strs_tlast (strs_o_tlast),
|
|
.m_axis_strs_tvalid(strs_o_tvalid),
|
|
.m_axis_strs_tready(strs_o_tready),
|
|
.data_err_stb (signal_data_err)
|
|
);
|
|
|
|
// Module to swap words in the payload and metadata depending on SW settings
|
|
chdr_data_swapper #( .CHDR_W(CHDR_W)) do_swap_i (
|
|
.clk (rfnoc_chdr_clk),
|
|
.rst (rfnoc_chdr_rst | reg_istrm_reset),
|
|
.payload_sw_buff(reg_istrm_cfg_pyld_sw_buff),
|
|
.mdata_sw_buff (reg_istrm_cfg_mdata_sw_buff),
|
|
.swap_endianness(reg_istrm_cfg_swap_endian),
|
|
.s_axis_tdata (axis_do_tdata),
|
|
.s_axis_tlast (axis_do_tlast),
|
|
.s_axis_tvalid (axis_do_tvalid),
|
|
.s_axis_tready (axis_do_tready),
|
|
.m_axis_tdata (axis_dos_tdata),
|
|
.m_axis_tlast (axis_dos_tlast),
|
|
.m_axis_tvalid (axis_dos_tvalid),
|
|
.m_axis_tready (axis_dos_tready)
|
|
);
|
|
|
|
// Optional DEMUX to split multiple single stream into multiple outputs
|
|
// Packets with an invalid (out of bounds) VC goes to port 0
|
|
if (NUM_DATA_O == 6'd1) begin
|
|
axi_fifo #(.WIDTH(CHDR_W+1), .SIZE(1)) axis_m_reg_i (
|
|
.clk(rfnoc_chdr_clk), .reset(rfnoc_chdr_rst | reg_istrm_reset), .clear(1'b0),
|
|
.i_tdata({axis_dos_tlast, axis_dos_tdata}),
|
|
.i_tvalid(axis_dos_tvalid), .i_tready(axis_dos_tready),
|
|
.o_tdata({m_axis_data_tlast, m_axis_data_tdata}),
|
|
.o_tvalid(m_axis_data_tvalid), .o_tready(m_axis_data_tready),
|
|
.space(), .occupied()
|
|
);
|
|
end else begin
|
|
wire [CHDR_W-1:0] data_header;
|
|
wire [5:0] data_vc = chdr_get_vc(data_header[63:0]);
|
|
axi_demux #(
|
|
.WIDTH(CHDR_W), .SIZE(NUM_DATA_O), .PRE_FIFO_SIZE(1), .POST_FIFO_SIZE(1)
|
|
) axis_m_demux_i (
|
|
.clk(rfnoc_chdr_clk), .reset(rfnoc_chdr_rst | reg_istrm_reset), .clear(1'b0),
|
|
.header(data_header),
|
|
.dest((data_vc < NUM_DATA_O) ? data_vc[$clog2(NUM_DATA_O)-1:0] : {$clog2(NUM_DATA_O){1'b0}}),
|
|
.i_tdata(axis_dos_tdata), .i_tlast(axis_dos_tlast),
|
|
.i_tvalid(axis_dos_tvalid), .i_tready(axis_dos_tready),
|
|
.o_tdata(m_axis_data_tdata), .o_tlast(m_axis_data_tlast),
|
|
.o_tvalid(m_axis_data_tvalid), .o_tready(m_axis_data_tready)
|
|
);
|
|
end
|
|
|
|
end else begin // if (AXIS_DATA_EN)
|
|
|
|
assign data_i_tready = 1'b1;
|
|
assign data_o_tdata = {CHDR_W{1'b0}};
|
|
assign data_o_tlast = 1'b0;
|
|
assign data_o_tvalid = 1'b0;
|
|
|
|
assign strs_i_tready = 1'b1;
|
|
assign strs_o_tdata = {CHDR_W{1'b0}};
|
|
assign strs_o_tlast = 1'b0;
|
|
assign strs_o_tvalid = 1'b0;
|
|
|
|
assign s_axis_data_tready = {NUM_DATA_I{1'b0}};
|
|
assign m_axis_data_tdata = {(CHDR_W*NUM_DATA_O){1'b0}};
|
|
assign m_axis_data_tlast = {NUM_DATA_O{1'b0}};
|
|
assign m_axis_data_tvalid = {NUM_DATA_O{1'b0}};
|
|
|
|
end endgenerate
|
|
|
|
// ---------------------------------------------------
|
|
// Control Path
|
|
// ---------------------------------------------------
|
|
generate if (AXIS_CTRL_EN) begin: ctrlpath
|
|
|
|
// Convert from a CHDR control packet to an AXIS control packet
|
|
chdr_to_axis_ctrl #(
|
|
.CHDR_W(CHDR_W), .THIS_PORTID(CTRL_XBAR_PORT)
|
|
) chdr_ctrl_adapter_i (
|
|
.rfnoc_chdr_clk (rfnoc_chdr_clk),
|
|
.rfnoc_chdr_rst (rfnoc_chdr_rst | reg_ctrl_reset),
|
|
.this_epid (reg_epid_self),
|
|
.s_rfnoc_chdr_tdata (ctrl_i_tdata),
|
|
.s_rfnoc_chdr_tlast (ctrl_i_tlast),
|
|
.s_rfnoc_chdr_tvalid(ctrl_i_tvalid),
|
|
.s_rfnoc_chdr_tready(ctrl_i_tready),
|
|
.m_rfnoc_chdr_tdata (ctrl_o_tdata),
|
|
.m_rfnoc_chdr_tlast (ctrl_o_tlast),
|
|
.m_rfnoc_chdr_tvalid(ctrl_o_tvalid),
|
|
.m_rfnoc_chdr_tready(ctrl_o_tready),
|
|
.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
|
|
.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
|
|
.s_rfnoc_ctrl_tdata (s_axis_ctrl_tdata),
|
|
.s_rfnoc_ctrl_tlast (s_axis_ctrl_tlast),
|
|
.s_rfnoc_ctrl_tvalid(s_axis_ctrl_tvalid),
|
|
.s_rfnoc_ctrl_tready(s_axis_ctrl_tready),
|
|
.m_rfnoc_ctrl_tdata (m_axis_ctrl_tdata),
|
|
.m_rfnoc_ctrl_tlast (m_axis_ctrl_tlast),
|
|
.m_rfnoc_ctrl_tvalid(m_axis_ctrl_tvalid),
|
|
.m_rfnoc_ctrl_tready(m_axis_ctrl_tready)
|
|
);
|
|
|
|
end else begin // if (AXIS_CTRL_EN)
|
|
|
|
assign ctrl_i_tready = 1'b1;
|
|
assign ctrl_o_tdata = {CHDR_W{1'b0}};
|
|
assign ctrl_o_tlast = 1'b0;
|
|
assign ctrl_o_tvalid = 1'b0;
|
|
|
|
assign s_axis_ctrl_tready = 1'b1;
|
|
assign m_axis_ctrl_tdata = 32'h0;
|
|
assign m_axis_ctrl_tlast = 1'b0;
|
|
assign m_axis_ctrl_tvalid = 1'b0;
|
|
|
|
end endgenerate
|
|
|
|
endmodule // chdr_stream_endpoint
|
|
|