22 lines
608 B
Systemverilog
22 lines
608 B
Systemverilog
//
|
|
// Copyright 2022 Ettus Research, A National Instruments Brand
|
|
//
|
|
// SPDX-License-Identifier: LGPL-3.0-or-later
|
|
//
|
|
// Header: rfnoc_image_core.vh (for n300)
|
|
//
|
|
// Description:
|
|
//
|
|
// This is the header file for the RFNoC Image Core.
|
|
//
|
|
// This file was automatically generated by the RFNoC image builder tool.
|
|
// Re-running that tool will overwrite this file!
|
|
//
|
|
// File generated on: 2022-03-29T22:54:30.972437
|
|
// Source: n300_rfnoc_image_core.yml
|
|
// Source SHA256: ff8842cde084161d27fda07e5835051fb4355b4579b933e944207a6e33031c3b
|
|
//
|
|
|
|
`define CHDR_WIDTH 64
|
|
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
|