7e59e9516d
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Original-commit: 7015f5ed2d495f3908773b7c7d74864d0cc3871a
74 lines
1.9 KiB
Verilog
74 lines
1.9 KiB
Verilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: pwr_supply_clk_gen
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//
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// Description:
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//
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// Generates a clock for one motherboard power supply.
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//
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// Parameters:
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//
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// BASE_ADDRESS : Base address for CtrlPort registers.
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// NUM_ADDRESSES : Number of bytes of address space to use.
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//
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`default_nettype none
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module pwr_supply_clk_gen#(
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parameter SOURCE_CLK_FREQ = 100_000_000,
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parameter TARGET_CLK_FREQ = 100_000
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) (
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// Base clock and reset
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input wire clk,
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input wire rst,
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// Power supply clocks
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output reg pwr_supply_clk
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);
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//-----------------------------------------------------------------------------
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// Counter Calculation / Definition
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//-----------------------------------------------------------------------------
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// Counter to generate the power supply switching clock
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// Assumption: the ratio between the generated clock and the source clock is
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// even, therefore we can produce a 50% DC clock output.
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localparam MAX_COUNT = SOURCE_CLK_FREQ / TARGET_CLK_FREQ / 2;
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localparam COUNTER_W = $clog2(MAX_COUNT);
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reg [COUNTER_W-1:0] counter = 0;
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//-----------------------------------------------------------------------------
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// Clock Generation
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//-----------------------------------------------------------------------------
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// This process implements a simple clock divider for the power supply
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// switcher.
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// SAFE COUNTER START! rst is a synchronous reset generated in the
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// clk domain; therefore, inherently safe.
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always @(posedge clk) begin
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if (rst) begin
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counter <= 0;
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pwr_supply_clk <= 1'b0;
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end
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else begin
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// Add one every cycle to the counter
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counter <= counter + 1'b1;
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// When the counter reaches its mid value, it is reset and the output clock
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// output is toggled.
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if (counter == MAX_COUNT-1) begin
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counter <= 0;
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pwr_supply_clk <= ~pwr_supply_clk;
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end
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end
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end
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endmodule
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`default_nettype wire
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