a1d7c252c2
Co-authored-by: Cherwa Vang <cherwa.vang@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Original-commit: 99b841c75aa91709090cbf4046bf51b7ffb4f612
91 lines
3.6 KiB
Makefile
91 lines
3.6 KiB
Makefile
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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GIT_HASH = $(shell ../../../../../tools/scripts/git-hash.sh)
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build: cpld_defaults ip
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@echo -ne "\n---- Make: Synthesis ...\n\n";
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@quartus_map zbx_top_cpld --verilog_macro="GIT_HASH=32'h$(GIT_HASH)";
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@echo -ne "\n\n---- Make: Implementation ...\n\n";
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@quartus_fit zbx_top_cpld;
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@echo -ne "\n\n---- Make: Analyzing timing ...\n\n";
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@quartus_sta zbx_top_cpld;
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@# grep for unconstrained path warning
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@grep "332102" output_files/zbx_top_cpld.sta.rpt; \
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if [ $$? -eq 0 ]; then false; else true; fi
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@# grep for timing closure critical warning
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@grep "332148" output_files/zbx_top_cpld.sta.rpt; \
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if [ $$? -eq 0 ]; then false; else true; fi
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@# expect no warnings
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@grep -iw "warning" output_files/zbx_top_cpld.sta.rpt; \
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if [ $$? -eq 0 ]; then false; else true; fi
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@# expect no critical warning except "review power analyzer report file"
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@grep -i "critical warning" output_files/* | grep -v 16562; \
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if [ $$? -eq 0 ]; then false; else true; fi
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@echo -ne "\n\n---- Make: Generating bitfile...\n\n";
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@quartus_asm zbx_top_cpld;
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@echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP enabled)...\n\n";
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@quartus_cpf --convert \
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--frequency 12.5MHz \
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--voltage 2.5 \
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--operation p \
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./output_files/zbx_top_cpld.pof ./output_files/zbx_top_cpld_isp_on.svf -o background_programming=on;
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@echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP disabled)...\n\n";
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@quartus_cpf --convert \
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--frequency 12.5MHz \
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--voltage 2.5 \
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--operation p \
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./output_files/zbx_top_cpld.pof ./output_files/zbx_top_cpld_isp_off.svf;
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@echo -ne "\n\n---- Make: Converting bitfile to rdp format...\n\n";
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@quartus_cpf -c raw_conversion.cof
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@echo -ne "\n\n---- Make: Copy final files...\n\n";
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@mkdir -p build
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@cp output_files/zbx_top_cpld.pof build/usrp_zbx_cpld.pof
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@cp output_files/zbx_top_cpld_isp_off.svf build/usrp_zbx_cpld.svf
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@cp output_files/zbx_top_cpld_isp_on.svf build/usrp_zbx_cpld_isp_on.svf
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@cp output_files/zbx_top_cpld_converted_cfm0_auto.rpd build/usrp_zbx_cpld.rpd
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@echo -ne "\n\n---- Make: ZBX CPLD ready!\n";
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@echo -ne " Use build/usrp_zbx_cpld.pof via JTAG programmer or\n"
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@echo -ne " build/usrp_zbx_cpld.svf (ISP off) via MB CPLD JTAG engine or\n"
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@echo -ne " build/usrp_zbx_cpld.rpd via reconfig engine or\n"
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@echo -ne " build/usrp_zbx_cpld_isp_on.rpd via MB CPLD JTAG engine.\n"
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clean:
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@echo -ne "\nCleaning ZBX CPLD...\n";
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@git clean -Xdf
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QSYS_PATH=$(subst \,/,$(QUARTUS_ROOTDIR))/sopc_builder/bin
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ROOT_DIR:=$(shell dirname $(realpath $(firstword $(MAKEFILE_LIST))))
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REGS_PY_FILE=$(ROOT_DIR)/../../../../../../../host/lib/ic_reg_maps/gen_zbx_cpld_regs.py
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REGS_PY_MODULE=register_endpoints/memory_init_files/zbx_cpld_regs_t.py
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$(REGS_PY_MODULE): $(REGS_PY_FILE)
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@python3 $(REGS_PY_FILE) $(REGS_PY_MODULE)
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# Using one of the files as a dependency (all files are generated at the same time)
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INIT_FILES := $(ROOT_DIR)/register_endpoints/memory_init_files/rx0_path_defaults.hex
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$(INIT_FILES): register_endpoints/memory_init_files/gen_defaults.py $(REGS_PY_MODULE)
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@python3 $(ROOT_DIR)/register_endpoints/memory_init_files/gen_defaults.py
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cpld_defaults: $(INIT_FILES)
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ip: ip/flash/on_chip_flash/simulation/on_chip_flash.v \
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ip/osc/osc/simulation/osc.v
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@make -C ../../../cpld ip
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ip/flash/on_chip_flash/simulation/on_chip_flash.v:
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$(QSYS_PATH)/qsys-generate ip/flash/on_chip_flash.qsys --simulation=VERILOG
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ip/osc/osc/simulation/osc.v:
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$(QSYS_PATH)/qsys-generate ip/osc/osc.qsys --simulation=VERILOG
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all: build
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.PHONY: all build clean ip
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