Wade Fife
7fa7ce1f81
Removes the CPU_W parameter from x4xx.v and the qsfp_wrapper files. The value of this parameter depends on the axi_eth_dma IP and therefore should not be changed. Original-commit: 84c49f40adc980e2968a6a844b4bdbb2d2d38c9c
334 lines
10 KiB
Systemverilog
334 lines
10 KiB
Systemverilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: x4xx_qsfp_wrapper_temp
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//
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// Description:
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//
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// Translation layer between Verilog and SystemVerilog for x4xx_qsfp_wrapper.
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//
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// Parameters:
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//
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// PROTOCOL : Indicates the protocol to use for each of the 4 QSFP
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// lanes. See x4xx_mgt_types.vh for possible values.
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// CHDR_W : CHDR width used by RFNoC on the FPGA
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// NET_CHDR_W : CHDR width used over the network connection
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// BYTE_MTU : Transport MTU in bytes
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// PORTNUM : Port number to distinguish multiple QSFP ports
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// NODE_INST : RFNoC transport adapter node instance for the first port
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// RFNOC_PROTOVER : RFNoC protocol version for IPv4 interface
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//
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`include "./x4xx_mgt_types.vh"
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module x4xx_qsfp_wrapper_temp #(
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parameter PROTOCOL0 = `MGT_Disabled,
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parameter PROTOCOL1 = `MGT_Disabled,
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parameter PROTOCOL2 = `MGT_Disabled,
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parameter PROTOCOL3 = `MGT_Disabled,
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parameter CHDR_W = 64,
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parameter NET_CHDR_W = CHDR_W,
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parameter BYTE_MTU = $clog2(8*1024),
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parameter [ 7:0] PORTNUM = 8'd0,
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parameter NODE_INST = 0,
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parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0}
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) (
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// Resets
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input logic areset,
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input logic bus_rst,
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input logic clk40_rst,
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// Clocks
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input logic refclk_p,
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input logic refclk_n,
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input logic clk100,
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input logic clk40,
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input logic bus_clk,
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// AXI-Lite
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input logic [39:0] s_axi_awaddr,
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input logic s_axi_awvalid,
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output logic s_axi_awready,
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input logic [31:0] s_axi_wdata,
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input logic [ 3:0] s_axi_wstrb,
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input logic s_axi_wvalid,
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output logic s_axi_wready,
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output logic [ 1:0] s_axi_bresp,
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output logic s_axi_bvalid,
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input logic s_axi_bready,
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input logic [39:0] s_axi_araddr,
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input logic s_axi_arvalid,
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output logic s_axi_arready,
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output logic [31:0] s_axi_rdata,
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output logic [ 1:0] s_axi_rresp,
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output logic s_axi_rvalid,
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input logic s_axi_rready,
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// MGT high-speed IO
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output logic [3:0] tx_p,
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output logic [3:0] tx_n,
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input logic [3:0] rx_p,
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input logic [3:0] rx_n,
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// CHDR router interface
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output logic [4*CHDR_W-1:0] e2v_tdata,
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output logic [ 3:0] e2v_tlast,
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output logic [ 3:0] e2v_tvalid,
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input logic [ 3:0] e2v_tready,
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input logic [4*CHDR_W-1:0] v2e_tdata,
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input logic [ 3:0] v2e_tlast,
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input logic [ 3:0] v2e_tvalid,
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output logic [ 3:0] v2e_tready,
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// Ethernet DMA AXI to CPU memory
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output logic [ 48:0] axi_hp_araddr,
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output logic [ 1:0] axi_hp_arburst,
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output logic [ 3:0] axi_hp_arcache,
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output logic [ 7:0] axi_hp_arlen,
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output logic [ 0:0] axi_hp_arlock,
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output logic [ 2:0] axi_hp_arprot,
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output logic [ 3:0] axi_hp_arqos,
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input logic axi_hp_arready,
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output logic [ 2:0] axi_hp_arsize,
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output logic axi_hp_arvalid,
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output logic [ 48:0] axi_hp_awaddr,
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output logic [ 1:0] axi_hp_awburst,
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output logic [ 3:0] axi_hp_awcache,
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output logic [ 7:0] axi_hp_awlen,
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output logic [ 0:0] axi_hp_awlock,
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output logic [ 2:0] axi_hp_awprot,
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output logic [ 3:0] axi_hp_awqos,
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input logic axi_hp_awready,
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output logic [ 2:0] axi_hp_awsize,
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output logic axi_hp_awvalid,
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output logic axi_hp_bready,
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input logic [ 1:0] axi_hp_bresp,
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input logic axi_hp_bvalid,
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input logic [127:0] axi_hp_rdata,
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input logic axi_hp_rlast,
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output logic axi_hp_rready,
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input logic [ 1:0] axi_hp_rresp,
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input logic axi_hp_rvalid,
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output logic [127:0] axi_hp_wdata,
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output logic axi_hp_wlast,
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input logic axi_hp_wready,
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output logic [ 15:0] axi_hp_wstrb,
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output logic axi_hp_wvalid,
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// Ethernet DMA IRQs
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output logic [3:0] eth_rx_irq,
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output logic [3:0] eth_tx_irq,
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// Misc.
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output logic rx_rec_clk_out,
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input logic [15:0] device_id,
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output logic [31:0] port_info_0,
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output logic [31:0] port_info_1,
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output logic [31:0] port_info_2,
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output logic [31:0] port_info_3,
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output logic [3:0] link_up,
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output logic [3:0] activity
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);
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import PkgAxiLite::*;
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`include "../../lib/axi4lite_sv/axi_lite.vh"
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`include "../../lib/axi4s_sv/axi4s.vh"
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//---------------------------------------------------------------------------
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// AXI Interfaces
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//---------------------------------------------------------------------------
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localparam CHDR_USER_W = $clog2(CHDR_W/8);
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// AXI-Stream for RFNoC CHDR
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AxiStreamIf #(.DATA_WIDTH(CHDR_W), .USER_WIDTH(CHDR_USER_W),
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.TKEEP(0), .TUSER(0))
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v2e[4] (bus_clk, bus_rst);
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AxiStreamIf #(.DATA_WIDTH(CHDR_W), .USER_WIDTH(CHDR_USER_W),
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.TKEEP(0), .TUSER(0))
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e2v[4] (bus_clk, bus_rst);
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// AXI-Lite register interface
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AxiLiteIf #(.DATA_WIDTH(32), .ADDR_WIDTH(40))
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s_axi (clk40, clk40_rst);
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// AXI (Full) for DMA back to CPU memory
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AxiIf #(.DATA_WIDTH(128), .ADDR_WIDTH(49))
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axi_hp (clk40, clk40_rst);
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logic [3:0][31:0] port_info;
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//---------------------------------------------------------------------------
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// Translate Signals to Interfaces
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//---------------------------------------------------------------------------
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always_comb begin
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port_info_0 = port_info[0];
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port_info_1 = port_info[1];
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port_info_2 = port_info[2];
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port_info_3 = port_info[3];
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//---------------------------------
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// s_axi
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//---------------------------------
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// Write channel
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s_axi.awaddr[39:18] = 0;
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s_axi.awaddr[17:0] = s_axi_awaddr[17:0]; // 256 KiB window
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s_axi.awvalid = s_axi_awvalid;
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s_axi_awready = s_axi.awready;
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s_axi.wdata = s_axi_wdata[31:0];
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s_axi.wstrb = s_axi_wstrb;
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s_axi.wvalid = s_axi_wvalid;
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s_axi_wready = s_axi.wready;
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s_axi_bresp = s_axi.bresp[1:0];
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s_axi_bvalid = s_axi.bvalid;
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s_axi.bready = s_axi_bready;
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// Read channel
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s_axi.araddr[39:18] = 0;
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s_axi.araddr[17:0] = s_axi_araddr[17:0]; // 256 KiB window
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s_axi.arvalid = s_axi_arvalid;
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s_axi_arready = s_axi.arready;
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s_axi_rdata[31:0] = s_axi.rdata;
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s_axi_rresp = s_axi.rresp[1:0];
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s_axi_rvalid = s_axi.rvalid;
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s_axi.rready = s_axi_rready;
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//---------------------------------
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// axi_hp
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//---------------------------------
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// Write channel
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axi_hp_awaddr = axi_hp.awaddr;
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axi_hp_awburst = axi_hp.awburst;
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axi_hp_awcache = axi_hp.awcache;
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axi_hp_awlen = axi_hp.awlen;
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axi_hp_awsize = axi_hp.awsize;
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axi_hp_awlock = axi_hp.awlock;
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axi_hp_awprot = axi_hp.awprot;
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axi_hp_awqos = axi_hp.awqos;
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axi_hp_awvalid = axi_hp.awvalid;
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axi_hp.awready = axi_hp_awready;
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axi_hp_wdata = axi_hp.wdata;
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axi_hp_wstrb = axi_hp.wstrb;
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axi_hp_wlast = axi_hp.wlast;
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axi_hp_wvalid = axi_hp.wvalid;
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axi_hp.wready = axi_hp_wready;
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axi_hp.bresp[1:0] = axi_hp_bresp;
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axi_hp.bvalid = axi_hp_bvalid;
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axi_hp_bready = axi_hp.bready;
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// Read channel
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axi_hp_araddr = axi_hp.araddr;
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axi_hp_arburst = axi_hp.arburst;
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axi_hp_arcache = axi_hp.arcache;
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axi_hp_arlen = axi_hp.arlen;
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axi_hp_arsize = axi_hp.arsize;
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axi_hp_arlock = axi_hp.arlock;
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axi_hp_arprot = axi_hp.arprot;
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axi_hp_arqos = axi_hp.arqos;
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axi_hp_arvalid = axi_hp.arvalid;
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axi_hp.arready = axi_hp_arready;
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axi_hp.rdata = axi_hp_rdata;
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axi_hp.rresp[1:0] = axi_hp_rresp;
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axi_hp.rlast = axi_hp_rlast;
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axi_hp.rvalid = axi_hp_rvalid;
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axi_hp_rready = axi_hp.rready;
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//---------------------------------
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// CHDR Links
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//---------------------------------
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e2v_tdata[1*CHDR_W-1:0*CHDR_W] = e2v[0].tdata;
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e2v_tlast[0] = e2v[0].tlast;
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e2v_tvalid[0] = e2v[0].tvalid;
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e2v[0].tready = e2v_tready[0];
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e2v_tdata[2*CHDR_W-1:1*CHDR_W] = e2v[1].tdata;
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e2v_tlast[1] = e2v[1].tlast;
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e2v_tvalid[1] = e2v[1].tvalid;
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e2v[1].tready = e2v_tready[1];
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e2v_tdata[3*CHDR_W-1:2*CHDR_W] = e2v[2].tdata;
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e2v_tlast[2] = e2v[2].tlast;
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e2v_tvalid[2] = e2v[2].tvalid;
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e2v[2].tready = e2v_tready[2];
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e2v_tdata[4*CHDR_W-1:3*CHDR_W] = e2v[3].tdata;
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e2v_tlast[3] = e2v[3].tlast;
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e2v_tvalid[3] = e2v[3].tvalid;
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e2v[3].tready = e2v_tready[3];
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v2e[0].tdata = v2e_tdata[1*CHDR_W-1:0*CHDR_W];
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v2e[0].tlast = v2e_tlast[0];
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v2e[0].tvalid = v2e_tvalid[0];
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v2e_tready[0] = v2e[0].tready;
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v2e[1].tdata = v2e_tdata[2*CHDR_W-1:1*CHDR_W];
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v2e[1].tlast = v2e_tlast[1];
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v2e[1].tvalid = v2e_tvalid[1];
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v2e_tready[1] = v2e[1].tready;
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v2e[2].tdata = v2e_tdata[3*CHDR_W-1:2*CHDR_W];
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v2e[2].tlast = v2e_tlast[2];
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v2e[2].tvalid = v2e_tvalid[2];
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v2e_tready[2] = v2e[2].tready;
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v2e[3].tdata = v2e_tdata[4*CHDR_W-1:3*CHDR_W];
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v2e[3].tlast = v2e_tlast[3];
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v2e[3].tvalid = v2e_tvalid[3];
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v2e_tready[3] = v2e[3].tready;
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end
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x4xx_qsfp_wrapper #(
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.PROTOCOL ({ PROTOCOL3, PROTOCOL2, PROTOCOL1, PROTOCOL0 }),
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.CHDR_W (CHDR_W),
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.NET_CHDR_W (NET_CHDR_W),
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.BYTE_MTU (BYTE_MTU),
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.PORTNUM (PORTNUM),
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.NODE_INST (NODE_INST),
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.RFNOC_PROTOVER (RFNOC_PROTOVER)
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) x4xx_qsfp_wrapper_i (
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.areset (areset),
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.refclk_p (refclk_p),
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.refclk_n (refclk_n),
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.bus_rst (bus_rst),
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.clk40_rst (clk40_rst),
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.clk100 (clk100),
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.bus_clk (bus_clk),
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.s_axi (s_axi),
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.tx_p (tx_p),
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.tx_n (tx_n),
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.rx_p (rx_p),
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.rx_n (rx_n),
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.e2v (e2v),
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.v2e (v2e),
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.axi_hp (axi_hp),
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.eth_tx_irq (eth_tx_irq),
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.eth_rx_irq (eth_rx_irq),
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.device_id (device_id),
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.rx_rec_clk_out (rx_rec_clk_out),
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.port_info (port_info),
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.link_up (link_up),
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.activity (activity)
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);
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endmodule
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