Wade Fife
2612487d43
Adds a 266.667 MHz compute engine clock and uses it instead of the radio clock for the DDC and DUC. Using a faster clock than the radio allows the DDC and DUC to drain after a stall in the data flow. Original-commit: ff55d406a02cc934a5c238d22c836bea08ade3d1
91 lines
4.2 KiB
Tcl
91 lines
4.2 KiB
Tcl
#
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# Copyright 2017 Ettus Research, A National Instruments Company
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# SPDX-License-Identifier: LGPL-3.0
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#
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# Timing analysis is performed in "/n3xx/doc/mb_timing.xlsx". See
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# the spreadsheet for more details and explanations.
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#*******************************************************************************
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## Motherboard Clocks
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# 10/20/25 MHz reference clock from rear panel connector. Constrain to the fastest
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# possible clock rate.
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set REF_CLK_PERIOD 40.00
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create_clock -name ref_clk -period $REF_CLK_PERIOD [get_ports FPGA_REFCLK_P]
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# 125 MHz RJ45 Ethernet clock
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create_clock -name ge_phy_clk -period 8.000 [get_ports ENET0_CLK125]
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# 156.25 MHz oscillator to MGT bank 110
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create_clock -name xge_clk -period 6.400 [get_ports MGT156MHZ_CLK1_P]
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# 125 MHz PLL for MG bank 109
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create_clock -name net_clk -period 8.000 [get_ports NETCLK_P]
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# Virtual clocks for constraining I/O (used below)
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create_clock -name async_in_clk -period 50.00
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create_clock -name async_out_clk -period 50.00
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#*******************************************************************************
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## Aliases for auto-generated clocks
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# Rename the PS clocks. These are originally declared in the PS7 IP block, but do not
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# have super descriptive names. We rename them here for additional clarity, and to match
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# the rest of the design.
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# First save off the input jitter setting for each, before we nuke the original clocks.
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set clk100_jitter [get_property INPUT_JITTER [get_clocks clk_fpga_0]]
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set clk40_jitter [get_property INPUT_JITTER [get_clocks clk_fpga_1]]
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set meas_clk_ref_jitter [get_property INPUT_JITTER [get_clocks clk_fpga_2]]
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set bus_clk_jitter [get_property INPUT_JITTER [get_clocks clk_fpga_3]]
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# Create the new clocks based on the old ones. This generates critical warnings that
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# we are completely rewriting the old clock definition... this is OK.
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create_clock -name clk100 \
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-period [get_property PERIOD [get_clocks clk_fpga_0]] \
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[get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_0]]]
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create_clock -name clk40 \
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-period [get_property PERIOD [get_clocks clk_fpga_1]] \
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[get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_1]]]
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create_clock -name meas_clk_ref \
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-period [get_property PERIOD [get_clocks clk_fpga_2]] \
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[get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_2]]]
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create_clock -name bus_clk \
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-period [get_property PERIOD [get_clocks clk_fpga_3]] \
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[get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_3]]]
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# Apply the jitter setting from the original clocks.
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set_input_jitter [get_clocks clk100] $clk100_jitter
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set_input_jitter [get_clocks clk40] $clk40_jitter
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set_input_jitter [get_clocks meas_clk_ref] $meas_clk_ref_jitter
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set_input_jitter [get_clocks bus_clk] $bus_clk_jitter
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# TDC Measurement Clock
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create_generated_clock -name meas_clk_fb [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_inst/CLKFBOUT}]
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create_generated_clock -name meas_clk [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_inst/CLKOUT0}]
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# CE Clock
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create_generated_clock -name ce_clk_fb [get_pins {n3xx_clocking_i/ce_clk_gen_i/CLKFBOUT}]
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create_generated_clock -name ce_clk [get_pins {n3xx_clocking_i/ce_clk_gen_i/CLKOUT0}]
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#*******************************************************************************
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## White Rabbit DAC
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# Constrain the DIN and NSYNC bits around the clock output. No readback.
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set WR_OUT_CLK [get_ports {WB_DAC_SCLK}]
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create_generated_clock -name wr_bus_clk \
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-source [get_pins [all_fanin -flat -only_cells -startpoints_only $WR_OUT_CLK]/C] \
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-divide_by 2 $WR_OUT_CLK
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#*******************************************************************************
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## Front Panel GPIO
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# These bits are driven from the DB-A radio clock. Although they are received async in
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# the outside world, they should be constrained in the FPGA to avoid any race
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# conditions. The best way to do this is a skew constraint across all the bits.
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set FP_GPIO_CLK [get_ports {FPGA_GPIO[0]}]
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create_generated_clock -name fp_gpio_bus_clk \
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-source [get_pins [all_fanin -flat -only_cells -startpoints_only $FP_GPIO_CLK]/C] \
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-divide_by 2 $FP_GPIO_CLK
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