This change causes HLS IP to be exported with a version of 1.0.0 instead of a date code. Due to a bug in Vivado, date codes after 0x7FFFFFFF (anything in 2022 or beyond) cause an error. Setting an explicit revision avoids this issue. See Xilinx AR 76960 for details. Original-commit: 51384afc2c5d4db9e2e45d97382edce8c8039b10
42 lines
1.4 KiB
Tcl
42 lines
1.4 KiB
Tcl
#
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# Copyright 2015 Ettus Research
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#
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# ---------------------------------------
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# Gather all external parameters
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# ---------------------------------------
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set part_name $::env(PART_NAME) ;# Full Xilinx part name
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set hls_ip_name $::env(HLS_IP_NAME) ;# High level synthesis IP name
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set hls_ip_srcs $::env(HLS_IP_SRCS) ;# High level synthesis IP source files
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if {[info exists env(HLS_IP_INCLUDES)]} {
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set hls_ip_inc $::env(HLS_IP_INCLUDES); # High level synthesis IP include directories
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} else {
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set hls_ip_inc {}
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}
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# ---------------------------------------
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# Vivado Commands
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# ---------------------------------------
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open_project $hls_ip_name
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open_solution "solution"
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set_part $part_name
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set_top $hls_ip_name
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puts "BUILDER: Using include location : $hls_ip_inc"
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foreach src_file $hls_ip_srcs {
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set src_ext [file extension $src_file ]
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if [expr [lsearch {.c .cpp .cc .h .hpp} $src_ext] >= 0] {
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puts "BUILDER: Adding C/C++ : $src_file"
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add_files $src_file -cflags "-I $hls_ip_inc"
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} elseif [expr [lsearch {.tcl} $src_ext] >= 0] {
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puts "BUILDER: Executing tcl script : $src_file"
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source $src_file
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} else {
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puts "BUILDER: \[WARNING\] File ignored!!!: $src_file"
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}
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}
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csynth_design
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puts "BUILDER: Setting IP export version to 1.0.0 to workaround Y2K22 bug (AR 76960)"
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export_design -format ip_catalog -version 1.0.0
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exit
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