Both files are a UHD 3 remnant and potentially confusing for UHD 4 codebase readers. Original-commit: b29af0ea0d340f37628f65e7b739fa1865d212a9
108 lines
2.2 KiB
Makefile
108 lines
2.2 KiB
Makefile
#
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# Copyright 2019 Ettus Research, A National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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##################################################
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# RFNoC Includes
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##################################################
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/xport/Makefile.srcs
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RFNOC_FRAMEWORK_SRCS = $(RFNOC_CORE_SRCS) $(RFNOC_XBAR_SRCS) $(RFNOC_UTIL_SRCS) $(RFNOC_XPORT_SRCS)
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##################################################
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# RFNoC Sources
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##################################################
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RFNOC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/, \
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chdr_fifo_large.v \
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axi_bit_reduce.v \
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null_source.v \
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split_stream.v \
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split_stream_fifo.v \
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conj.v \
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delay_fifo.v \
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delay_type2.v \
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delay_type3.v \
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delay_type4.v \
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complex_to_magsq.v \
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phase_accum.v \
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complex_invert.v \
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periodic_framer.v \
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moving_sum.v \
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counter.v \
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ram_to_fifo.v \
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const.v \
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const_sreg.v \
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cmul.v \
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cadd.v \
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keep_one_in_n.v \
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vector_iir.v \
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addsub.v \
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axi_pipe.v \
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multiply.v \
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mult.v \
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mult_add.v \
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mult_rc.v \
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mult_add_rc.v \
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fft_shift.v \
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axi_pipe_join.v \
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axi_pipe_mac.v \
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axi_round_and_clip_complex.v \
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axi_round_complex.v \
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axi_clip_complex.v \
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axi_join.v \
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axi_sync.v \
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split_complex.v \
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axi_round_and_clip.v \
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join_complex.v \
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axi_round.v \
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axi_clip.v \
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axi_clip_unsigned.v \
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axi_serializer.v \
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axi_deserializer.v \
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axi_packer.v \
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complex_to_mag_approx.v \
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file_source.v \
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fosphor/delay.v \
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fosphor/fifo_srl.v \
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fosphor/rng.v \
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fosphor/f15_avg.v \
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fosphor/f15_binmap.v \
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fosphor/f15_core.v \
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fosphor/f15_eoseq.v \
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fosphor/f15_histo_mem.v \
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fosphor/f15_line_mem.v \
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fosphor/f15_logpwr.v \
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fosphor/f15_maxhold.v \
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fosphor/f15_packetizer.v \
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fosphor/f15_rise_decay.v \
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fosphor/f15_wf_agg.v \
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fosphor/axi_logpwr.v \
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cvita_hdr_parser.v \
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cvita_hdr_encoder.v \
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cvita_hdr_decoder.v \
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cvita_hdr_modify.v \
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axi_async_stream.v \
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axi_rate_change.v \
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axi_tag_time.v \
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axi_drop_partial_packet.v \
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ddc.v \
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duc.v \
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cic_decimate.v \
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cic_interpolate.v \
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sine_tone.v \
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axi_fir_filter.v \
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fir_filter_slice.v \
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axi_fir_filter_dec.v \
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addsub.vhd \
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dds_freq_tune.v \
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dds_freq_tune_duc.v \
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dds_timed.v \
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dds_wrapper.v \
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datapath_gatekeeper.v \
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))
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