Files
b210-k7-fpga/top/x400/ip/axi_inter_4x64_512_bd/Makefile.inc
T
Wade Fife 9a4a9645ad fpga: x400: Add axi_inter_4x64_512_bd IP
Original-commit: 129440913803de793b82ddbd7b6f5605dacb8aa3
2022-02-07 13:08:11 -07:00

29 lines
1014 B
Makefile

#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI_INTER_4X64_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_4x64_512_bd/, \
axi_inter_4x64_512_bd.tcl \
)
IP_AXI_INTER_4X64_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_4x64_512_bd/, \
axi_inter_4x64_512_bd.tcl \
)
IP_AXI_INTER_4X64_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_4x64_512_bd/, \
axi_inter_4x64_512_bd/axi_inter_4x64_512_bd.bd \
)
BD_AXI_INTER_4X64_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_4x64_512_bd/, \
axi_inter_4x64_512_bd.bd.out \
axi_inter_4x64_512_bd/axi_inter_4x64_512_bd_ooc.xdc \
axi_inter_4x64_512_bd/synth/axi_inter_4x64_512_bd.v \
)
$(IP_AXI_INTER_4X64_512_BD_SRCS) $(BD_AXI_INTER_4X64_512_BD_OUTS) $(IP_AXI_INTER_4X64_512_BDTCL_SRCS): $(IP_AXI_INTER_4X64_512_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,axi_inter_4x64_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)